arch/mips/include/asm/sgi/heart.h

Source file repositories/reference/linux-study-clean/arch/mips/include/asm/sgi/heart.h

File Facts

System
Linux kernel
Corpus path
arch/mips/include/asm/sgi/heart.h
Extension
.h
Size
12666 bytes
Lines
324
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ip30_heart_regs {		/* 0x0ff00000 */
	u64 mode;			/* +  0x00000 */
	/* Memory */
	u64 sdram_mode;			/* +  0x00008 */
	u64 mem_refresh;		/* +  0x00010 */
	u64 mem_req_arb;		/* +  0x00018 */
	union {
		u64 q[HEART_MEMORY_BANKS];	/* readq() */
		u32 l[HEART_MEMORY_BANKS * 2];	/* readl() */
	} mem_cfg;			/* +  0x00020 */
	/* Flow control (gfx?) */
	u64 fc_mode;			/* +  0x00040 */
	u64 fc_timer_limit;		/* +  0x00048 */
	u64 fc_addr[2];			/* +  0x00050 */
	u64 fc_credit_cnt[2];		/* +  0x00060 */
	u64 fc_timer[2];		/* +  0x00070 */
	/* Status */
	u64 status;			/* +  0x00080 */
	/* Bus error */
	u64 bus_err_addr;		/* +  0x00088 */
	u64 bus_err_misc;		/* +  0x00090 */
	/* Memory error */
	u64 mem_err_addr;		/* +  0x00098 */
	u64 mem_err_data;		/* +  0x000a0 */
	/* Misc */
	u64 piur_acc_err;		/* +  0x000a8 */
	u64 mlan_clock_div;		/* +  0x000b0 */
	u64 mlan_ctrl;			/* +  0x000b8 */
	u64 __pad0[0x01e8];		/* +  0x000c0 + 0x0f40 */
	/* Undefined */
	u64 undefined;			/* +  0x01000 */
	u64 __pad1[0x1dff];		/* +  0x01008 + 0xeff8 */
	/* Interrupts */
	u64 imr[HEART_MAX_CPUS];	/* +  0x10000 */
	u64 set_isr;			/* +  0x10020 */
	u64 clear_isr;			/* +  0x10028 */
	u64 isr;			/* +  0x10030 */
	u64 imsr;			/* +  0x10038 */
	u64 cause;			/* +  0x10040 */
	u64 __pad2[0x1ff7];		/* +  0x10048 + 0xffb8 */
	/* Timer */
	u64 count;			/* +  0x20000 */
	u64 __pad3[0x1fff];		/* +  0x20008 + 0xfff8 */
	u64 compare;			/* +  0x30000 */
	u64 __pad4[0x1fff];		/* +  0x30008 + 0xfff8 */
	u64 trigger;			/* +  0x40000 */
	u64 __pad5[0x1fff];		/* +  0x40008 + 0xfff8 */
	/* Misc */
	u64 cpuid;			/* +  0x50000 */
	u64 __pad6[0x1fff];		/* +  0x50008 + 0xfff8 */
	u64 sync;			/* +  0x60000 */
};


/* For timer-related bits. */
#define HEART_NS_PER_CYCLE	80
#define HEART_CYCLES_PER_SEC	(NSEC_PER_SEC / HEART_NS_PER_CYCLE)


/*
 * XXX: Everything below this comment will either go away or be cleaned
 *      up to fit in better with Linux.  A lot of the bit definitions for
 *      HEART were derived from IRIX's sys/RACER/heart.h header file.
 */

/* HEART Masks */
#define HEART_ATK_MASK		0x0007ffffffffffff	/* HEART attack mask */
#define HEART_ACK_ALL_MASK	0xffffffffffffffff	/* Ack everything */
#define HEART_CLR_ALL_MASK	0x0000000000000000	/* Clear all */
#define HEART_BR_ERR_MASK	0x7ff8000000000000	/* BRIDGE error mask */
#define HEART_CPU0_ERR_MASK	0x8ff8000000000000	/* CPU0 error mask */
#define HEART_CPU1_ERR_MASK	0x97f8000000000000	/* CPU1 error mask */
#define HEART_CPU2_ERR_MASK	0xa7f8000000000000	/* CPU2 error mask */
#define HEART_CPU3_ERR_MASK	0xc7f8000000000000	/* CPU3 error mask */
#define HEART_ERR_MASK		0x1ff			/* HEART error mask */
#define HEART_ERR_MASK_START	51			/* HEART error start */
#define HEART_ERR_MASK_END	63			/* HEART error end */

/* Bits in the HEART_MODE register. */
#define HM_PROC_DISABLE_SHFT		60
#define HM_PROC_DISABLE_MSK		(0xfUL << HM_PROC_DISABLE_SHFT)
#define HM_PROC_DISABLE(x)		(0x1UL << (x) + HM_PROC_DISABLE_SHFT)
#define HM_MAX_PSR			(0x7UL << 57)
#define HM_MAX_IOSR			(0x7UL << 54)
#define HM_MAX_PEND_IOSR		(0x7UL << 51)
#define HM_TRIG_SRC_SEL_MSK		(0x7UL << 48)
#define HM_TRIG_HEART_EXC		(0x0UL << 48)
#define HM_TRIG_REG_BIT			(0x1UL << 48)
#define HM_TRIG_SYSCLK			(0x2UL << 48)
#define HM_TRIG_MEMCLK_2X		(0x3UL << 48)

Annotation

Implementation Notes