arch/mips/include/asm/sgi/hpc3.h

Source file repositories/reference/linux-study-clean/arch/mips/include/asm/sgi/hpc3.h

File Facts

System
Linux kernel
Corpus path
arch/mips/include/asm/sgi/hpc3.h
Extension
.h
Size
14470 bytes
Lines
318
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

struct hpc_dma_desc {
	u32 pbuf;	/* physical address of data buffer */
	u32 cntinfo;	/* counter and info bits */
#define HPCDMA_EOX	0x80000000 /* last desc in chain for tx */
#define HPCDMA_EOR	0x80000000 /* last desc in chain for rx */
#define HPCDMA_EOXP	0x40000000 /* end of packet for tx */
#define HPCDMA_EORP	0x40000000 /* end of packet for rx */
#define HPCDMA_XIE	0x20000000 /* irq generated when at end of this desc */
#define HPCDMA_XIU	0x01000000 /* Tx buffer in use by CPU. */
#define HPCDMA_EIPC	0x00ff0000 /* SEEQ ethernet special xternal bytecount */
#define HPCDMA_ETXD	0x00008000 /* set to one by HPC when packet tx'd */
#define HPCDMA_OWN	0x00004000 /* Denotes ring buffer ownership on rx */
#define HPCDMA_BCNT	0x00003fff /* size in bytes of this dma buffer */

	u32 pnext;	/* paddr of next hpc_dma_desc if any */
};

/* The set of regs for each HPC3 PBUS DMA channel. */
struct hpc3_pbus_dmacregs {
	volatile u32 pbdma_bptr;	/* pbus dma channel buffer ptr */
	volatile u32 pbdma_dptr;	/* pbus dma channel desc ptr */
	u32 _unused0[0x1000/4 - 2];	/* padding */
	volatile u32 pbdma_ctrl;	/* pbus dma channel control register has
					 * completely different meaning for read
					 * compared with write */
	/* read */
#define HPC3_PDMACTRL_INT	0x00000001 /* interrupt (cleared after read) */
#define HPC3_PDMACTRL_ISACT	0x00000002 /* channel active */
	/* write */
#define HPC3_PDMACTRL_SEL	0x00000002 /* little endian transfer */
#define HPC3_PDMACTRL_RCV	0x00000004 /* direction is receive */
#define HPC3_PDMACTRL_FLSH	0x00000008 /* enable flush for receive DMA */
#define HPC3_PDMACTRL_ACT	0x00000010 /* start dma transfer */
#define HPC3_PDMACTRL_LD	0x00000020 /* load enable for ACT */
#define HPC3_PDMACTRL_RT	0x00000040 /* Use realtime GIO bus servicing */
#define HPC3_PDMACTRL_HW	0x0000ff00 /* DMA High-water mark */
#define HPC3_PDMACTRL_FB	0x003f0000 /* Ptr to beginning of fifo */
#define HPC3_PDMACTRL_FE	0x3f000000 /* Ptr to end of fifo */

	u32 _unused1[0x1000/4 - 1];	/* padding */
};

/* The HPC3 SCSI registers, this does not include external ones. */
struct hpc3_scsiregs {
	volatile u32 cbptr;	/* current dma buffer ptr, diagnostic use only */
	volatile u32 ndptr;	/* next dma descriptor ptr */
	u32 _unused0[0x1000/4 - 2];	/* padding */
	volatile u32 bcd;	/* byte count info */
#define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */
#define HPC3_SBCD_XIE	  0x00004000 /* Send IRQ when done with cur buf */
#define HPC3_SBCD_EOX	  0x00008000 /* Indicates this is last buf in chain */

	volatile u32 ctrl;    /* control register */
#define HPC3_SCTRL_IRQ	  0x01 /* IRQ asserted, either dma done or parity */
#define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */
#define HPC3_SCTRL_DIR	  0x04 /* DMA direction, 1=dev2mem 0=mem2dev */
#define HPC3_SCTRL_FLUSH  0x08 /* Tells HPC3 to flush scsi fifos */
#define HPC3_SCTRL_ACTIVE 0x10 /* SCSI DMA channel is active */
#define HPC3_SCTRL_AMASK  0x20 /* DMA active inhibits PIO */
#define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */
#define HPC3_SCTRL_PERR	  0x80 /* Bad parity on HPC3 iface to scsi controller */

	volatile u32 gfptr;	/* current GIO fifo ptr */
	volatile u32 dfptr;	/* current device fifo ptr */
	volatile u32 dconfig;	/* DMA configuration register */
#define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */
#define HPC3_SDCFG_D1	0x00006 /* Cycles to spend in D1 state */
#define HPC3_SDCFG_D2	0x00038 /* Cycles to spend in D2 state */
#define HPC3_SDCFG_D3	0x001c0 /* Cycles to spend in D3 state */
#define HPC3_SDCFG_HWAT 0x00e00 /* DMA high water mark */
#define HPC3_SDCFG_HW	0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
#define HPC3_SDCFG_SWAP 0x02000 /* Byte swap all DMA accesses */
#define HPC3_SDCFG_EPAR 0x04000 /* Enable parity checking for DMA */
#define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */
#define HPC3_SDCFG_ERLY 0x30000 /* hd_dreq behavior control bits */

	volatile u32 pconfig;	/* PIO configuration register */
#define HPC3_SPCFG_P3	0x0003 /* Cycles to spend in P3 state */
#define HPC3_SPCFG_P2W	0x001c /* Cycles to spend in P2 state for writes */
#define HPC3_SPCFG_P2R	0x01e0 /* Cycles to spend in P2 state for reads */
#define HPC3_SPCFG_P1	0x0e00 /* Cycles to spend in P1 state */
#define HPC3_SPCFG_HW	0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
#define HPC3_SPCFG_SWAP 0x2000 /* Byte swap all PIO accesses */
#define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */
#define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */

	u32 _unused1[0x1000/4 - 6];	/* padding */
};

/* SEEQ ethernet HPC3 registers, only one seeq per HPC3. */

Annotation

Implementation Notes