arch/mips/include/asm/sgi/mc.h

Source file repositories/reference/linux-study-clean/arch/mips/include/asm/sgi/mc.h

File Facts

System
Linux kernel
Corpus path
arch/mips/include/asm/sgi/mc.h
Extension
.h
Size
9479 bytes
Lines
232
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

struct sgimc_regs {
	u32 _unused0;
	volatile u32 cpuctrl0;	/* CPU control register 0, readwrite */
#define SGIMC_CCTRL0_REFS	0x0000000f /* REFS mask */
#define SGIMC_CCTRL0_EREFRESH	0x00000010 /* Memory refresh enable */
#define SGIMC_CCTRL0_EPERRGIO	0x00000020 /* GIO parity error enable */
#define SGIMC_CCTRL0_EPERRMEM	0x00000040 /* Main mem parity error enable */
#define SGIMC_CCTRL0_EPERRCPU	0x00000080 /* CPU bus parity error enable */
#define SGIMC_CCTRL0_WDOG	0x00000100 /* Watchdog timer enable */
#define SGIMC_CCTRL0_SYSINIT	0x00000200 /* System init bit */
#define SGIMC_CCTRL0_GFXRESET	0x00000400 /* Graphics interface reset */
#define SGIMC_CCTRL0_EISALOCK	0x00000800 /* Lock CPU from memory for EISA */
#define SGIMC_CCTRL0_EPERRSCMD	0x00001000 /* SysCMD bus parity error enable */
#define SGIMC_CCTRL0_IENAB	0x00002000 /* Allow interrupts from MC */
#define SGIMC_CCTRL0_ESNOOP	0x00004000 /* Snooping I/O enable */
#define SGIMC_CCTRL0_EPROMWR	0x00008000 /* Prom writes from cpu enable */
#define SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */
#define SGIMC_CCTRL0_LENDIAN	0x00020000 /* Put MC in little-endian mode */
#define SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */
#define SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */
#define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */
#define SGIMC_CCTRL0_GIOBTOB	0x08000000 /* Allow GIO back to back writes */
	u32 _unused1;
	volatile u32 cpuctrl1;	/* CPU control register 1, readwrite */
#define SGIMC_CCTRL1_EGIOTIMEO	0x00000010 /* GIO bus timeout enable */
#define SGIMC_CCTRL1_FIXEDEHPC	0x00001000 /* Fixed HPC endianness */
#define SGIMC_CCTRL1_LITTLEHPC	0x00002000 /* Little endian HPC */
#define SGIMC_CCTRL1_FIXEDEEXP0 0x00004000 /* Fixed EXP0 endianness */
#define SGIMC_CCTRL1_LITTLEEXP0 0x00008000 /* Little endian EXP0 */
#define SGIMC_CCTRL1_FIXEDEEXP1 0x00010000 /* Fixed EXP1 endianness */
#define SGIMC_CCTRL1_LITTLEEXP1 0x00020000 /* Little endian EXP1 */

	u32 _unused2;
	volatile u32 watchdogt; /* Watchdog reg rdonly, write clears */

	u32 _unused3;
	volatile u32 systemid;	/* MC system ID register, readonly */
#define SGIMC_SYSID_MASKREV	0x0000000f /* Revision of MC controller */
#define SGIMC_SYSID_EPRESENT	0x00000010 /* Indicates presence of EISA bus */

	u32 _unused4[3];
	volatile u32 divider;	/* Divider reg for RPSS */

	u32 _unused5;
	u32 eeprom;		/* EEPROM byte reg for r4k */
#define SGIMC_EEPROM_PRE	0x00000001 /* eeprom chip PRE pin assertion */
#define SGIMC_EEPROM_CSEL	0x00000002 /* Active high, eeprom chip select */
#define SGIMC_EEPROM_SECLOCK	0x00000004 /* EEPROM serial clock */
#define SGIMC_EEPROM_SDATAO	0x00000008 /* Serial EEPROM data-out */
#define SGIMC_EEPROM_SDATAI	0x00000010 /* Serial EEPROM data-in */

	u32 _unused6[3];
	volatile u32 rcntpre;	/* Preload refresh counter */

	u32 _unused7;
	volatile u32 rcounter;	/* Readonly refresh counter */

	u32 _unused8[13];
	volatile u32 giopar;	/* Parameter word for GIO64 */
#define SGIMC_GIOPAR_HPC64	0x00000001 /* HPC talks to GIO using 64-bits */
#define SGIMC_GIOPAR_GFX64	0x00000002 /* GFX talks to GIO using 64-bits */
#define SGIMC_GIOPAR_EXP064	0x00000004 /* EXP(slot0) talks using 64-bits */
#define SGIMC_GIOPAR_EXP164	0x00000008 /* EXP(slot1) talks using 64-bits */
#define SGIMC_GIOPAR_EISA64	0x00000010 /* EISA bus talks 64-bits to GIO */
#define SGIMC_GIOPAR_HPC264	0x00000020 /* 2nd HPX talks 64-bits to GIO */
#define SGIMC_GIOPAR_RTIMEGFX	0x00000040 /* GFX device has realtime attr */
#define SGIMC_GIOPAR_RTIMEEXP0	0x00000080 /* EXP(slot0) has realtime attr */
#define SGIMC_GIOPAR_RTIMEEXP1	0x00000100 /* EXP(slot1) has realtime attr */
#define SGIMC_GIOPAR_MASTEREISA 0x00000200 /* EISA bus can act as bus master */
#define SGIMC_GIOPAR_ONEBUS	0x00000400 /* Exists one GIO64 pipelined bus */
#define SGIMC_GIOPAR_MASTERGFX	0x00000800 /* GFX can act as a bus master */
#define SGIMC_GIOPAR_MASTEREXP0 0x00001000 /* EXP(slot0) can bus master */
#define SGIMC_GIOPAR_MASTEREXP1 0x00002000 /* EXP(slot1) can bus master */
#define SGIMC_GIOPAR_PLINEEXP0	0x00004000 /* EXP(slot0) has pipeline attr */
#define SGIMC_GIOPAR_PLINEEXP1	0x00008000 /* EXP(slot1) has pipeline attr */

	u32 _unused9;
	volatile u32 cputp;	/* CPU bus arb time period */

	u32 _unused10[3];
	volatile u32 lbursttp;	/* Time period for long bursts */

	/* MC chip can drive up to 4 bank 4 SIMMs each. All SIMMs in bank must
	 * be the same size. The size encoding for supported SIMMs is below */
	u32 _unused11[9];
	volatile u32 mconfig0;	/* Memory config register zero */
	u32 _unused12;
	volatile u32 mconfig1;	/* Memory config register one */
#define SGIMC_MCONFIG_BASEADDR	0x000000ff /* Base address of bank*/
#define SGIMC_MCONFIG_RMASK	0x00001f00 /* Ram config bitmask */

Annotation

Implementation Notes