arch/mips/include/asm/sibyte/sb1250_int.h

Source file repositories/reference/linux-study-clean/arch/mips/include/asm/sibyte/sb1250_int.h

File Facts

System
Linux kernel
Corpus path
arch/mips/include/asm/sibyte/sb1250_int.h
Extension
.h
Size
8922 bytes
Lines
236
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _SB1250_INT_H
#define _SB1250_INT_H

#include <asm/sibyte/sb1250_defs.h>

/*  *********************************************************************
    *  Interrupt Mapper Constants
    ********************************************************************* */

/*
 * Interrupt sources (Table 4-8, UM 0.2)
 *
 * First, the interrupt numbers.
 */

#define K_INT_SOURCES		    64

#define K_INT_WATCHDOG_TIMER_0	    0
#define K_INT_WATCHDOG_TIMER_1	    1
#define K_INT_TIMER_0		    2
#define K_INT_TIMER_1		    3
#define K_INT_TIMER_2		    4
#define K_INT_TIMER_3		    5
#define K_INT_SMB_0		    6
#define K_INT_SMB_1		    7
#define K_INT_UART_0		    8
#define K_INT_UART_1		    9
#define K_INT_SER_0		    10
#define K_INT_SER_1		    11
#define K_INT_PCMCIA		    12
#define K_INT_ADDR_TRAP		    13
#define K_INT_PERF_CNT		    14
#define K_INT_TRACE_FREEZE	    15
#define K_INT_BAD_ECC		    16
#define K_INT_COR_ECC		    17
#define K_INT_IO_BUS		    18
#define K_INT_MAC_0		    19
#define K_INT_MAC_1		    20
#define K_INT_MAC_2		    21
#define K_INT_DM_CH_0		    22
#define K_INT_DM_CH_1		    23
#define K_INT_DM_CH_2		    24
#define K_INT_DM_CH_3		    25
#define K_INT_MBOX_0		    26
#define K_INT_MBOX_1		    27
#define K_INT_MBOX_2		    28
#define K_INT_MBOX_3		    29
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define K_INT_CYCLE_CP0_INT	    30
#define K_INT_CYCLE_CP1_INT	    31
#endif /* 1250 PASS2 || 112x PASS1 */
#define K_INT_GPIO_0		    32
#define K_INT_GPIO_1		    33
#define K_INT_GPIO_2		    34
#define K_INT_GPIO_3		    35
#define K_INT_GPIO_4		    36
#define K_INT_GPIO_5		    37
#define K_INT_GPIO_6		    38
#define K_INT_GPIO_7		    39
#define K_INT_GPIO_8		    40
#define K_INT_GPIO_9		    41
#define K_INT_GPIO_10		    42
#define K_INT_GPIO_11		    43
#define K_INT_GPIO_12		    44
#define K_INT_GPIO_13		    45
#define K_INT_GPIO_14		    46
#define K_INT_GPIO_15		    47
#define K_INT_LDT_FATAL		    48
#define K_INT_LDT_NONFATAL	    49
#define K_INT_LDT_SMI		    50
#define K_INT_LDT_NMI		    51
#define K_INT_LDT_INIT		    52
#define K_INT_LDT_STARTUP	    53
#define K_INT_LDT_EXT		    54
#define K_INT_PCI_ERROR		    55
#define K_INT_PCI_INTA		    56
#define K_INT_PCI_INTB		    57
#define K_INT_PCI_INTC		    58
#define K_INT_PCI_INTD		    59
#define K_INT_SPARE_2		    60
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define K_INT_MAC_0_CH1		    61
#define K_INT_MAC_1_CH1		    62
#define K_INT_MAC_2_CH1		    63
#endif /* 1250 PASS2 || 112x PASS1 */

/*
 * Mask values for each interrupt
 */

Annotation

Implementation Notes