arch/mips/include/asm/sibyte/sb1250_regs.h

Source file repositories/reference/linux-study-clean/arch/mips/include/asm/sibyte/sb1250_regs.h

File Facts

System
Linux kernel
Corpus path
arch/mips/include/asm/sibyte/sb1250_regs.h
Extension
.h
Size
32129 bytes
Lines
881
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _SB1250_REGS_H
#define _SB1250_REGS_H

#include <asm/sibyte/sb1250_defs.h>


/*  *********************************************************************
    *  Some general notes:
    *
    *  For the most part, when there is more than one peripheral
    *  of the same type on the SOC, the constants below will be
    *  offsets from the base of each peripheral.  For example,
    *  the MAC registers are described as offsets from the first
    *  MAC register, and there will be a MAC_REGISTER() macro
    *  to calculate the base address of a given MAC.
    *
    *  The information in this file is based on the SB1250 SOC
    *  manual version 0.2, July 2000.
    ********************************************************************* */


/*  *********************************************************************
    * Memory Controller Registers
    ********************************************************************* */

/*
 * XXX: can't remove MC base 0 if 112x, since it's used by other macros,
 * since there is one reg there (but it could get its addr/offset constant).
 */

#if SIBYTE_HDR_FEATURE_1250_112x		/* This MC only on 1250 & 112x */
#define A_MC_BASE_0		    0x0010051000
#define A_MC_BASE_1		    0x0010052000
#define MC_REGISTER_SPACING	    0x1000

#define A_MC_BASE(ctlid)	    ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0)
#define A_MC_REGISTER(ctlid, reg)    (A_MC_BASE(ctlid)+(reg))

#define R_MC_CONFIG		    0x0000000100
#define R_MC_DRAMCMD		    0x0000000120
#define R_MC_DRAMMODE		    0x0000000140
#define R_MC_TIMING1		    0x0000000160
#define R_MC_TIMING2		    0x0000000180
#define R_MC_CS_START		    0x00000001A0
#define R_MC_CS_END		    0x00000001C0
#define R_MC_CS_INTERLEAVE	    0x00000001E0
#define S_MC_CS_STARTEND	    16

#define R_MC_CSX_BASE		    0x0000000200
#define R_MC_CSX_ROW		    0x0000000000	/* relative to CSX_BASE, above */
#define R_MC_CSX_COL		    0x0000000020	/* relative to CSX_BASE, above */
#define R_MC_CSX_BA		    0x0000000040	/* relative to CSX_BASE, above */
#define MC_CSX_SPACING		    0x0000000060	/* relative to CSX_BASE, above */

#define R_MC_CS0_ROW		    0x0000000200
#define R_MC_CS0_COL		    0x0000000220
#define R_MC_CS0_BA		    0x0000000240
#define R_MC_CS1_ROW		    0x0000000260
#define R_MC_CS1_COL		    0x0000000280
#define R_MC_CS1_BA		    0x00000002A0
#define R_MC_CS2_ROW		    0x00000002C0
#define R_MC_CS2_COL		    0x00000002E0
#define R_MC_CS2_BA		    0x0000000300
#define R_MC_CS3_ROW		    0x0000000320
#define R_MC_CS3_COL		    0x0000000340
#define R_MC_CS3_BA		    0x0000000360
#define R_MC_CS_ATTR		    0x0000000380
#define R_MC_TEST_DATA		    0x0000000400
#define R_MC_TEST_ECC		    0x0000000420
#define R_MC_MCLK_CFG		    0x0000000500

#endif	/* 1250 & 112x */

/*  *********************************************************************
    * L2 Cache Control Registers
    ********************************************************************* */

#if SIBYTE_HDR_FEATURE_1250_112x	/* This L2C only on 1250/112x */

#define A_L2_READ_TAG		    0x0010040018
#define A_L2_ECC_TAG		    0x0010040038
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_L2_READ_MISC		    0x0010040058
#endif /* 1250 PASS3 || 112x PASS1 */
#define A_L2_WAY_DISABLE	    0x0010041000
#define A_L2_MAKEDISABLE(x)	    (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8))
#define A_L2_MGMT_TAG_BASE	    0x00D0000000

#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_L2_CACHE_DISABLE	   0x0010042000

Annotation

Implementation Notes