arch/mips/include/asm/sn/sn0/hubni.h

Source file repositories/reference/linux-study-clean/arch/mips/include/asm/sn/sn0/hubni.h

File Facts

System
Linux kernel
Corpus path
arch/mips/include/asm/sn/sn0/hubni.h
Extension
.h
Size
9525 bytes
Lines
264
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _ASM_SGI_SN0_HUBNI_H
#define _ASM_SGI_SN0_HUBNI_H

#ifndef __ASSEMBLER__
#include <linux/types.h>
#endif

/*
 * Hub Network Interface registers
 *
 * All registers in this file are subject to change until Hub chip tapeout.
 */

#define NI_BASE			0x600000
#define NI_BASE_TABLES		0x630000

#define NI_STATUS_REV_ID	0x600000 /* Hub network status, rev, and ID */
#define NI_PORT_RESET		0x600008 /* Reset the network interface	    */
#define NI_PROTECTION		0x600010 /* NI register access permissions  */
#define NI_GLOBAL_PARMS		0x600018 /* LLP parameters		    */
#define NI_SCRATCH_REG0		0x600100 /* Scratch register 0 (64 bits)    */
#define NI_SCRATCH_REG1		0x600108 /* Scratch register 1 (64 bits)    */
#define NI_DIAG_PARMS		0x600110 /* Parameters for diags	    */

#define NI_VECTOR_PARMS		0x600200 /* Vector PIO routing parameters   */
#define NI_VECTOR		0x600208 /* Vector PIO route		    */
#define NI_VECTOR_DATA		0x600210 /* Vector PIO data		    */
#define NI_VECTOR_STATUS	0x600300 /* Vector PIO return status	    */
#define NI_RETURN_VECTOR	0x600308 /* Vector PIO return vector	    */
#define NI_VECTOR_READ_DATA	0x600310 /* Vector PIO read data	    */
#define NI_VECTOR_CLEAR		0x600380 /* Vector PIO read & clear status  */

#define NI_IO_PROTECT		0x600400 /* PIO protection bits		    */
#define NI_IO_PROT_OVRRD	0x600408 /* PIO protection bit override	    */

#define NI_AGE_CPU0_MEMORY	0x600500 /* CPU 0 memory age control	    */
#define NI_AGE_CPU0_PIO		0x600508 /* CPU 0 PIO age control	    */
#define NI_AGE_CPU1_MEMORY	0x600510 /* CPU 1 memory age control	    */
#define NI_AGE_CPU1_PIO		0x600518 /* CPU 1 PIO age control	    */
#define NI_AGE_GBR_MEMORY	0x600520 /* GBR memory age control	    */
#define NI_AGE_GBR_PIO		0x600528 /* GBR PIO age control		    */
#define NI_AGE_IO_MEMORY	0x600530 /* IO memory age control	    */
#define NI_AGE_IO_PIO		0x600538 /* IO PIO age control		    */
#define NI_AGE_REG_MIN		NI_AGE_CPU0_MEMORY
#define NI_AGE_REG_MAX		NI_AGE_IO_PIO

#define NI_PORT_PARMS		0x608000 /* LLP Parameters		    */
#define NI_PORT_ERROR		0x608008 /* LLP Errors			    */
#define NI_PORT_ERROR_CLEAR	0x608088 /* Clear the error bits	    */

#define NI_META_TABLE0		0x638000 /* First meta routing table entry  */
#define NI_META_TABLE(_x)	(NI_META_TABLE0 + (8 * (_x)))
#define NI_META_ENTRIES		32

#define NI_LOCAL_TABLE0		0x638100 /* First local routing table entry */
#define NI_LOCAL_TABLE(_x)	(NI_LOCAL_TABLE0 + (8 * (_x)))
#define NI_LOCAL_ENTRIES	16

/*
 * NI_STATUS_REV_ID mask and shift definitions
 * Have to use UINT64_CAST instead of 'L' suffix, for assembler.
 */

#define NSRI_8BITMODE_SHFT	30
#define NSRI_8BITMODE_MASK	(UINT64_CAST 0x1 << 30)
#define NSRI_LINKUP_SHFT	29
#define NSRI_LINKUP_MASK	(UINT64_CAST 0x1 << 29)
#define NSRI_DOWNREASON_SHFT	28		/* 0=failed, 1=never came   */
#define NSRI_DOWNREASON_MASK	(UINT64_CAST 0x1 << 28) /*    out of reset. */
#define NSRI_MORENODES_SHFT	18
#define NSRI_MORENODES_MASK	(UINT64_CAST 1 << 18)	/* Max. # of nodes  */
#define	 MORE_MEMORY		0
#define	 MORE_NODES		1
#define NSRI_REGIONSIZE_SHFT	17
#define NSRI_REGIONSIZE_MASK	(UINT64_CAST 1 << 17)	/* Granularity	    */
#define	 REGIONSIZE_FINE	1
#define	 REGIONSIZE_COARSE	0
#define NSRI_NODEID_SHFT	8
#define NSRI_NODEID_MASK	(UINT64_CAST 0x1ff << 8)/* Node (Hub) ID    */
#define NSRI_REV_SHFT		4
#define NSRI_REV_MASK		(UINT64_CAST 0xf << 4)	/* Chip Revision    */
#define NSRI_CHIPID_SHFT	0
#define NSRI_CHIPID_MASK	(UINT64_CAST 0xf)	/* Chip type ID	    */

/*
 * In fine mode, each node is a region.	 In coarse mode, there are
 * eight nodes per region.
 */
#define NASID_TO_FINEREG_SHFT	0
#define NASID_TO_COARSEREG_SHFT 3

Annotation

Implementation Notes