arch/mips/include/asm/sni.h

Source file repositories/reference/linux-study-clean/arch/mips/include/asm/sni.h

File Facts

System
Linux kernel
Corpus path
arch/mips/include/asm/sni.h
Extension
.h
Size
7439 bytes
Lines
244
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __ASM_SNI_H
#define __ASM_SNI_H

#include <linux/irqreturn.h>

extern unsigned int sni_brd_type;

#define SNI_BRD_10		   2
#define SNI_BRD_10NEW		   3
#define SNI_BRD_TOWER_OASIC	   4
#define SNI_BRD_MINITOWER	   5
#define SNI_BRD_PCI_TOWER	   6
#define SNI_BRD_RM200		   7
#define SNI_BRD_PCI_MTOWER	   8
#define SNI_BRD_PCI_DESKTOP	   9
#define SNI_BRD_PCI_TOWER_CPLUS	  10
#define SNI_BRD_PCI_MTOWER_CPLUS  11

/* RM400 cpu types */
#define SNI_CPU_M8021		0x01
#define SNI_CPU_M8030		0x04
#define SNI_CPU_M8031		0x06
#define SNI_CPU_M8034		0x0f
#define SNI_CPU_M8037		0x07
#define SNI_CPU_M8040		0x05
#define SNI_CPU_M8043		0x09
#define SNI_CPU_M8050		0x0b
#define SNI_CPU_M8053		0x0d

#define SNI_PORT_BASE		CKSEG1ADDR(0xb4000000)

#ifndef __MIPSEL__
/*
 * ASIC PCI registers for big endian configuration.
 */
#define PCIMT_UCONF		CKSEG1ADDR(0xbfff0004)
#define PCIMT_IOADTIMEOUT2	CKSEG1ADDR(0xbfff000c)
#define PCIMT_IOMEMCONF		CKSEG1ADDR(0xbfff0014)
#define PCIMT_IOMMU		CKSEG1ADDR(0xbfff001c)
#define PCIMT_IOADTIMEOUT1	CKSEG1ADDR(0xbfff0024)
#define PCIMT_DMAACCESS		CKSEG1ADDR(0xbfff002c)
#define PCIMT_DMAHIT		CKSEG1ADDR(0xbfff0034)
#define PCIMT_ERRSTATUS		CKSEG1ADDR(0xbfff003c)
#define PCIMT_ERRADDR		CKSEG1ADDR(0xbfff0044)
#define PCIMT_SYNDROME		CKSEG1ADDR(0xbfff004c)
#define PCIMT_ITPEND		CKSEG1ADDR(0xbfff0054)
#define	 IT_INT2		0x01
#define	 IT_INTD		0x02
#define	 IT_INTC		0x04
#define	 IT_INTB		0x08
#define	 IT_INTA		0x10
#define	 IT_EISA		0x20
#define	 IT_SCSI		0x40
#define	 IT_ETH			0x80
#define PCIMT_IRQSEL		CKSEG1ADDR(0xbfff005c)
#define PCIMT_TESTMEM		CKSEG1ADDR(0xbfff0064)
#define PCIMT_ECCREG		CKSEG1ADDR(0xbfff006c)
#define PCIMT_CONFIG_ADDRESS	CKSEG1ADDR(0xbfff0074)
#define PCIMT_ASIC_ID		CKSEG1ADDR(0xbfff007c)	/* read */
#define PCIMT_SOFT_RESET	CKSEG1ADDR(0xbfff007c)	/* write */
#define PCIMT_PIA_OE		CKSEG1ADDR(0xbfff0084)
#define PCIMT_PIA_DATAOUT	CKSEG1ADDR(0xbfff008c)
#define PCIMT_PIA_DATAIN	CKSEG1ADDR(0xbfff0094)
#define PCIMT_CACHECONF		CKSEG1ADDR(0xbfff009c)
#define PCIMT_INVSPACE		CKSEG1ADDR(0xbfff00a4)
#else
/*
 * ASIC PCI registers for little endian configuration.
 */
#define PCIMT_UCONF		CKSEG1ADDR(0xbfff0000)
#define PCIMT_IOADTIMEOUT2	CKSEG1ADDR(0xbfff0008)
#define PCIMT_IOMEMCONF		CKSEG1ADDR(0xbfff0010)
#define PCIMT_IOMMU		CKSEG1ADDR(0xbfff0018)
#define PCIMT_IOADTIMEOUT1	CKSEG1ADDR(0xbfff0020)
#define PCIMT_DMAACCESS		CKSEG1ADDR(0xbfff0028)
#define PCIMT_DMAHIT		CKSEG1ADDR(0xbfff0030)
#define PCIMT_ERRSTATUS		CKSEG1ADDR(0xbfff0038)
#define PCIMT_ERRADDR		CKSEG1ADDR(0xbfff0040)
#define PCIMT_SYNDROME		CKSEG1ADDR(0xbfff0048)
#define PCIMT_ITPEND		CKSEG1ADDR(0xbfff0050)
#define	 IT_INT2		0x01
#define	 IT_INTD		0x02
#define	 IT_INTC		0x04
#define	 IT_INTB		0x08
#define	 IT_INTA		0x10
#define	 IT_EISA		0x20
#define	 IT_SCSI		0x40
#define	 IT_ETH			0x80
#define PCIMT_IRQSEL		CKSEG1ADDR(0xbfff0058)
#define PCIMT_TESTMEM		CKSEG1ADDR(0xbfff0060)

Annotation

Implementation Notes