arch/mips/include/asm/sync.h

Source file repositories/reference/linux-study-clean/arch/mips/include/asm/sync.h

File Facts

System
Linux kernel
Corpus path
arch/mips/include/asm/sync.h
Extension
.h
Size
7824 bytes
Lines
210
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __MIPS_ASM_SYNC_H__
#define __MIPS_ASM_SYNC_H__

/*
 * sync types are defined by the MIPS64 Instruction Set documentation in Volume
 * II-A of the MIPS Architecture Reference Manual, which can be found here:
 *
 *   https://www.mips.com/?do-download=the-mips64-instruction-set-v6-06
 *
 * Two types of barrier are provided:
 *
 *   1) Completion barriers, which ensure that a memory operation has actually
 *      completed & often involve stalling the CPU pipeline to do so.
 *
 *   2) Ordering barriers, which only ensure that affected memory operations
 *      won't be reordered in the CPU pipeline in a manner that violates the
 *      restrictions imposed by the barrier.
 *
 * Ordering barriers can be more efficient than completion barriers, since:
 *
 *   a) Ordering barriers only require memory access instructions which precede
 *      them in program order (older instructions) to reach a point in the
 *      load/store datapath beyond which reordering is not possible before
 *      allowing memory access instructions which follow them (younger
 *      instructions) to be performed.  That is, older instructions don't
 *      actually need to complete - they just need to get far enough that all
 *      other coherent CPUs will observe their completion before they observe
 *      the effects of younger instructions.
 *
 *   b) Multiple variants of ordering barrier are provided which allow the
 *      effects to be restricted to different combinations of older or younger
 *      loads or stores. By way of example, if we only care that stores older
 *      than a barrier are observed prior to stores that are younger than a
 *      barrier & don't care about the ordering of loads then the 'wmb'
 *      ordering barrier can be used. Limiting the barrier's effects to stores
 *      allows loads to continue unaffected & potentially allows the CPU to
 *      make progress faster than if younger loads had to wait for older stores
 *      to complete.
 */

/*
 * No sync instruction at all; used to allow code to nullify the effect of the
 * __SYNC() macro without needing lots of #ifdefery.
 */
#define __SYNC_none	-1

/*
 * A full completion barrier; all memory accesses appearing prior to this sync
 * instruction in program order must complete before any memory accesses
 * appearing after this sync instruction in program order.
 */
#define __SYNC_full	0x00

/*
 * For now we use a full completion barrier to implement all sync types, until
 * we're satisfied that lightweight ordering barriers defined by MIPSr6 are
 * sufficient to uphold our desired memory model.
 */
#define __SYNC_aq	__SYNC_full
#define __SYNC_rl	__SYNC_full
#define __SYNC_mb	__SYNC_full

/*
 * ...except on Cavium Octeon CPUs, which have been using the 'wmb' ordering
 * barrier since 2010 & omit 'rmb' barriers because the CPUs don't perform
 * speculative reads.
 */
#ifdef CONFIG_CPU_CAVIUM_OCTEON
# define __SYNC_rmb	__SYNC_none
# define __SYNC_wmb	0x04
#else
# define __SYNC_rmb	__SYNC_full
# define __SYNC_wmb	__SYNC_full
#endif

/*
 * A GINV sync is a little different; it doesn't relate directly to loads or
 * stores, but instead causes synchronization of an icache or TLB global
 * invalidation operation triggered by the ginvi or ginvt instructions
 * respectively. In cases where we need to know that a ginvi or ginvt operation
 * has been performed by all coherent CPUs, we must issue a sync instruction of
 * this type. Once this instruction graduates all coherent CPUs will have
 * observed the invalidation.
 */
#define __SYNC_ginv	0x14

/* Trivial; indicate that we always need this sync instruction. */
#define __SYNC_always	(1 << 0)

/*

Annotation

Implementation Notes