arch/mips/include/asm/vdso/processor.h

File Facts

System

Linux kernel

Corpus path

arch/mips/include/asm/vdso/processor.h

Extension

.h

Size

747 bytes

Lines

28

Domain

Architecture Layer

Bucket

arch/mips

Inferred role

Architecture Layer: implementation source

Status

source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef __ASM_VDSO_PROCESSOR_H
#define __ASM_VDSO_PROCESSOR_H

#ifndef __ASSEMBLER__

#ifdef CONFIG_CPU_LOONGSON64
/*
 * Loongson-3's SFB (Store-Fill-Buffer) may buffer writes indefinitely when a
 * tight read loop is executed, because reads take priority over writes & the
 * hardware (incorrectly) doesn't ensure that writes will eventually occur.
 *
 * Since spin loops of any kind should have a cpu_relax() in them, force an SFB
 * flush from cpu_relax() such that any pending writes will become visible as
 * expected.
 */
#define cpu_relax()	smp_mb()
#else
#define cpu_relax()	barrier()
#endif

#endif /* __ASSEMBLER__ */

#endif /* __ASM_VDSO_PROCESSOR_H */

Annotation

• Atlas domain: Architecture Layer / arch/mips.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.