arch/mips/kernel/cevt-ds1287.c
Source file repositories/reference/linux-study-clean/arch/mips/kernel/cevt-ds1287.c
File Facts
- System
- Linux kernel
- Corpus path
arch/mips/kernel/cevt-ds1287.c- Extension
.c- Size
- 2374 bytes
- Lines
- 123
- Domain
- Architecture Layer
- Bucket
- arch/mips
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/clockchips.hlinux/init.hlinux/interrupt.hlinux/mc146818rtc.hlinux/irq.hasm/ds1287.hasm/time.h
Detected Declarations
function Copyrightfunction ds1287_set_base_clockfunction ds1287_set_next_eventfunction ds1287_shutdownfunction ds1287_set_periodicfunction ds1287_event_handlerfunction ds1287_interruptfunction ds1287_clockevent_init
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* DS1287 clockevent driver
*
* Copyright (C) 2008 Yoichi Yuasa <yuasa@linux-mips.org>
*/
#include <linux/clockchips.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/mc146818rtc.h>
#include <linux/irq.h>
#include <asm/ds1287.h>
#include <asm/time.h>
int ds1287_timer_state(void)
{
return (CMOS_READ(RTC_REG_C) & RTC_PF) != 0;
}
int ds1287_set_base_clock(unsigned int hz)
{
u8 rate;
switch (hz) {
case 128:
rate = 0x9;
break;
case 256:
rate = 0x8;
break;
case 1024:
rate = 0x6;
break;
default:
return -EINVAL;
}
CMOS_WRITE(RTC_REF_CLCK_32KHZ | rate, RTC_REG_A);
return 0;
}
static int ds1287_set_next_event(unsigned long delta,
struct clock_event_device *evt)
{
return -EINVAL;
}
static int ds1287_shutdown(struct clock_event_device *evt)
{
u8 val;
spin_lock(&rtc_lock);
val = CMOS_READ(RTC_REG_B);
val &= ~RTC_PIE;
CMOS_WRITE(val, RTC_REG_B);
spin_unlock(&rtc_lock);
return 0;
}
static int ds1287_set_periodic(struct clock_event_device *evt)
{
u8 val;
spin_lock(&rtc_lock);
val = CMOS_READ(RTC_REG_B);
val |= RTC_PIE;
CMOS_WRITE(val, RTC_REG_B);
spin_unlock(&rtc_lock);
return 0;
}
static void ds1287_event_handler(struct clock_event_device *dev)
{
}
static struct clock_event_device ds1287_clockevent = {
.name = "ds1287",
.features = CLOCK_EVT_FEAT_PERIODIC,
.set_next_event = ds1287_set_next_event,
.set_state_shutdown = ds1287_shutdown,
.set_state_periodic = ds1287_set_periodic,
.tick_resume = ds1287_shutdown,
.event_handler = ds1287_event_handler,
};
Annotation
- Immediate include surface: `linux/clockchips.h`, `linux/init.h`, `linux/interrupt.h`, `linux/mc146818rtc.h`, `linux/irq.h`, `asm/ds1287.h`, `asm/time.h`.
- Detected declarations: `function Copyright`, `function ds1287_set_base_clock`, `function ds1287_set_next_event`, `function ds1287_shutdown`, `function ds1287_set_periodic`, `function ds1287_event_handler`, `function ds1287_interrupt`, `function ds1287_clockevent_init`.
- Atlas domain: Architecture Layer / arch/mips.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.