arch/mips/kernel/cpu-probe.c

Source file repositories/reference/linux-study-clean/arch/mips/kernel/cpu-probe.c

File Facts

System
Linux kernel
Corpus path
arch/mips/kernel/cpu-probe.c
Extension
.c
Size
53635 bytes
Lines
2090
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

if (flags & FTLB_SET_PROB) {
			config &= ~(3 << MTI_CONF6_FTLBP_SHIFT);
			config |= calculate_ftlb_probability(c)
				  << MTI_CONF6_FTLBP_SHIFT;
		}

		write_c0_config6(config);
		back_to_back_c0_hazard();
		break;
	case CPU_I6400:
	case CPU_I6500:
		/* There's no way to disable the FTLB */
		if (!(flags & FTLB_EN))
			return 1;
		return 0;
	case CPU_LOONGSON64:
		/* Flush ITLB, DTLB, VTLB and FTLB */
		write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
			      LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
		/* Loongson-3 cores use Config6 to enable the FTLB */
		config = read_c0_config6();
		if (flags & FTLB_EN)
			/* Enable FTLB */
			write_c0_config6(config & ~LOONGSON_CONF6_FTLBDIS);
		else
			/* Disable FTLB */
			write_c0_config6(config | LOONGSON_CONF6_FTLBDIS);
		break;
	default:
		return 1;
	}

	return 0;
}

static int mm_config(struct cpuinfo_mips *c)
{
	unsigned int config0, update, mm;

	config0 = read_c0_config();
	mm = config0 & MIPS_CONF_MM;

	/*
	 * It's implementation dependent what type of write-merge is supported
	 * and whether it can be enabled/disabled. If it is settable lets make
	 * the merging allowed by default. Some platforms might have
	 * write-through caching unsupported. In this case just ignore the
	 * CP0.Config.MM bit field value.
	 */
	switch (c->cputype) {
	case CPU_24K:
	case CPU_34K:
	case CPU_74K:
	case CPU_P5600:
	case CPU_P6600:
		c->options |= MIPS_CPU_MM_FULL;
		update = MIPS_CONF_MM_FULL;
		break;
	case CPU_1004K:
	case CPU_1074K:
	case CPU_INTERAPTIV:
	case CPU_PROAPTIV:
		mm = 0;
		fallthrough;
	default:
		update = 0;
		break;
	}

	if (update) {
		config0 = (config0 & ~MIPS_CONF_MM) | update;
		write_c0_config(config0);
	} else if (mm == MIPS_CONF_MM_SYSAD) {
		c->options |= MIPS_CPU_MM_SYSAD;
	} else if (mm == MIPS_CONF_MM_FULL) {
		c->options |= MIPS_CPU_MM_FULL;
	}

	return 0;
}

static inline unsigned int decode_config0(struct cpuinfo_mips *c)
{
	unsigned int config0;
	int isa, mt;

	config0 = read_c0_config();

	/*
	 * Look for Standard TLB or Dual VTLB and FTLB

Annotation

Implementation Notes