arch/mips/kernel/vpe-mt.c
Source file repositories/reference/linux-study-clean/arch/mips/kernel/vpe-mt.c
File Facts
- System
- Linux kernel
- Corpus path
arch/mips/kernel/vpe-mt.c- Extension
.c- Size
- 11224 bytes
- Lines
- 520
- Domain
- Architecture Layer
- Bucket
- arch/mips
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/device.hlinux/fs.hlinux/slab.hlinux/export.hasm/mipsregs.hasm/mipsmtregs.hasm/mips_mt.hasm/vpe.h
Detected Declarations
function vpe_runfunction cleanup_tcfunction vpe_startfunction vpe_stopfunction vpe_freefunction store_killfunction ntcs_showfunction ntcs_storefunction vpe_device_releasefunction vpe_module_initfunction vpe_module_exitexport vpe_allocexport vpe_startexport vpe_stopexport vpe_free
Annotated Snippet
err = device_add(&vpe_device);
if (err) {
pr_err("Adding vpe_device failed\n");
goto out_class;
}
local_irq_save(flags);
mtflags = dmt();
vpflags = dvpe();
/* Put MVPE's into 'configuration state' */
set_c0_mvpcontrol(MVPCONTROL_VPC);
val = read_c0_mvpconf0();
hw_tcs = (val & MVPCONF0_PTC) + 1;
hw_vpes = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
for (tc = aprp_cpu_index(); tc < hw_tcs; tc++) {
/*
* Must re-enable multithreading temporarily or in case we
* reschedule send IPIs or similar we might hang.
*/
clear_c0_mvpcontrol(MVPCONTROL_VPC);
evpe(vpflags);
emt(mtflags);
local_irq_restore(flags);
t = alloc_tc(tc);
if (!t) {
err = -ENOMEM;
goto out_dev;
}
local_irq_save(flags);
mtflags = dmt();
vpflags = dvpe();
set_c0_mvpcontrol(MVPCONTROL_VPC);
/* VPE's */
if (tc < hw_tcs) {
settc(tc);
v = alloc_vpe(tc);
if (v == NULL) {
pr_warn("VPE: unable to allocate VPE\n");
goto out_reenable;
}
v->ntcs = hw_tcs - aprp_cpu_index();
/* add the tc to the list of this vpe's tc's. */
list_add(&t->tc, &v->tc);
/* deactivate all but vpe0 */
if (tc >= aprp_cpu_index()) {
unsigned long tmp = read_vpe_c0_vpeconf0();
tmp &= ~VPECONF0_VPA;
/* master VPE */
tmp |= VPECONF0_MVP;
write_vpe_c0_vpeconf0(tmp);
}
/* disable multi-threading with TC's */
write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() &
~VPECONTROL_TE);
if (tc >= vpelimit) {
/*
* Set config to be the same as vpe0,
* particularly kseg0 coherency alg
*/
write_vpe_c0_config(read_c0_config());
}
}
/* TC's */
t->pvpe = v; /* set the parent vpe */
if (tc >= aprp_cpu_index()) {
unsigned long tmp;
settc(tc);
/*
* A TC that is bound to any other VPE gets bound to
* VPE0, ideally I'd like to make it homeless but it
* doesn't appear to let me bind a TC to a non-existent
* VPE. Which is perfectly reasonable.
*
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/device.h`, `linux/fs.h`, `linux/slab.h`, `linux/export.h`, `asm/mipsregs.h`, `asm/mipsmtregs.h`, `asm/mips_mt.h`.
- Detected declarations: `function vpe_run`, `function cleanup_tc`, `function vpe_start`, `function vpe_stop`, `function vpe_free`, `function store_kill`, `function ntcs_show`, `function ntcs_store`, `function vpe_device_release`, `function vpe_module_init`.
- Atlas domain: Architecture Layer / arch/mips.
- Implementation status: integration implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.