arch/mips/kvm/vz.c
Source file repositories/reference/linux-study-clean/arch/mips/kvm/vz.c
File Facts
- System
- Linux kernel
- Corpus path
arch/mips/kvm/vz.c- Extension
.c- Size
- 87519 bytes
- Lines
- 3326
- Domain
- Architecture Layer
- Bucket
- arch/mips
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Touches user memory; correctness depends on fault-safe copying and privilege boundary handling.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/errno.hlinux/err.hlinux/module.hlinux/preempt.hlinux/vmalloc.hasm/cacheflush.hasm/cacheops.hasm/cmpxchg.hasm/fpu.hasm/hazards.hasm/inst.hasm/mmu_context.hasm/r4kcache.hasm/time.hasm/tlb.hasm/tlbex.hlinux/kvm_host.hinterrupt.hloongson_regs.htrace.h
Detected Declarations
function kvm_vz_read_gc0_ebasefunction kvm_vz_write_gc0_ebasefunction kvm_vz_config_guest_wrmaskfunction kvm_vz_config1_guest_wrmaskfunction kvm_vz_config2_guest_wrmaskfunction kvm_vz_config3_guest_wrmaskfunction kvm_vz_config4_guest_wrmaskfunction kvm_vz_config5_guest_wrmaskfunction kvm_vz_config6_guest_wrmaskfunction kvm_vz_config_user_wrmaskfunction kvm_vz_config1_user_wrmaskfunction kvm_vz_config2_user_wrmaskfunction kvm_vz_config3_user_wrmaskfunction kvm_vz_config4_user_wrmaskfunction kvm_vz_config5_user_wrmaskfunction kvm_vz_config6_user_wrmaskfunction kvm_vz_gva_to_gpa_cbfunction kvm_vz_queue_irqfunction kvm_vz_dequeue_irqfunction kvm_vz_queue_timer_int_cbfunction kvm_vz_dequeue_timer_int_cbfunction kvm_vz_queue_io_int_cbfunction kvm_vz_dequeue_io_int_cbfunction kvm_vz_irq_deliver_cbfunction kvm_vz_irq_clear_cbfunction kvm_vz_should_use_htimerfunction _kvm_vz_restore_stimerfunction _kvm_vz_restore_htimerfunction kvm_vz_restore_timerfunction kvm_vz_acquire_htimerfunction _kvm_vz_save_htimerfunction kvm_vz_save_timerfunction kvm_vz_lose_htimerfunction is_eva_accessfunction is_eva_am_mappedfunction kvm_vz_gva_to_gpafunction kvm_vz_badvaddr_to_gpafunction kvm_trap_vz_no_handlerfunction mips_process_maarfunction kvm_write_maarifunction kvm_vz_gpsi_cop0function kvm_vz_gpsi_cachefunction kvm_vz_gpsi_lwc2function kvm_trap_vz_handle_gpsifunction kvm_trap_vz_handle_gsfcfunction kvm_trap_vz_handle_ghfcfunction kvm_trap_vz_handle_hcfunction kvm_trap_vz_no_handler_guest_exit
Annotated Snippet
if (cpu_has_guestctl2) {
if (!(read_c0_guestctl2() & (irq << 14)))
clear_c0_guestctl2(irq);
} else {
clear_gc0_cause(irq);
}
break;
case MIPS_EXC_INT_IO_1:
case MIPS_EXC_INT_IO_2:
case MIPS_EXC_INT_IPI_1:
case MIPS_EXC_INT_IPI_2:
/* Clear GuestCtl2.VIP irq if not using Hardware Clear */
if (cpu_has_guestctl2) {
if (!(read_c0_guestctl2() & (irq << 14)))
clear_c0_guestctl2(irq);
} else {
clear_gc0_cause(irq);
}
break;
default:
break;
}
clear_bit(priority, &vcpu->arch.pending_exceptions_clr);
return 1;
}
/*
* VZ guest timer handling.
*/
/**
* kvm_vz_should_use_htimer() - Find whether to use the VZ hard guest timer.
* @vcpu: Virtual CPU.
*
* Returns: true if the VZ GTOffset & real guest CP0_Count should be used
* instead of software emulation of guest timer.
* false otherwise.
*/
static bool kvm_vz_should_use_htimer(struct kvm_vcpu *vcpu)
{
if (kvm_mips_count_disabled(vcpu))
return false;
/* Chosen frequency must match real frequency */
if (mips_hpt_frequency != vcpu->arch.count_hz)
return false;
/* We don't support a CP0_GTOffset with fewer bits than CP0_Count */
if (current_cpu_data.gtoffset_mask != 0xffffffff)
return false;
return true;
}
/**
* _kvm_vz_restore_stimer() - Restore soft timer state.
* @vcpu: Virtual CPU.
* @compare: CP0_Compare register value, restored by caller.
* @cause: CP0_Cause register to restore.
*
* Restore VZ state relating to the soft timer. The hard timer can be enabled
* later.
*/
static void _kvm_vz_restore_stimer(struct kvm_vcpu *vcpu, u32 compare,
u32 cause)
{
/*
* Avoid spurious counter interrupts by setting Guest CP0_Count to just
* after Guest CP0_Compare.
*/
write_c0_gtoffset(compare - read_c0_count());
back_to_back_c0_hazard();
write_gc0_cause(cause);
}
/**
* _kvm_vz_restore_htimer() - Restore hard timer state.
* @vcpu: Virtual CPU.
* @compare: CP0_Compare register value, restored by caller.
* @cause: CP0_Cause register to restore.
*
* Restore hard timer Guest.Count & Guest.Cause taking care to preserve the
* value of Guest.CP0_Cause.TI while restoring Guest.CP0_Cause.
*/
static void _kvm_vz_restore_htimer(struct kvm_vcpu *vcpu,
u32 compare, u32 cause)
Annotation
- Immediate include surface: `linux/errno.h`, `linux/err.h`, `linux/module.h`, `linux/preempt.h`, `linux/vmalloc.h`, `asm/cacheflush.h`, `asm/cacheops.h`, `asm/cmpxchg.h`.
- Detected declarations: `function kvm_vz_read_gc0_ebase`, `function kvm_vz_write_gc0_ebase`, `function kvm_vz_config_guest_wrmask`, `function kvm_vz_config1_guest_wrmask`, `function kvm_vz_config2_guest_wrmask`, `function kvm_vz_config3_guest_wrmask`, `function kvm_vz_config4_guest_wrmask`, `function kvm_vz_config5_guest_wrmask`, `function kvm_vz_config6_guest_wrmask`, `function kvm_vz_config_user_wrmask`.
- Atlas domain: Architecture Layer / arch/mips.
- Implementation status: source implementation candidate.
- This snippet crosses the user/kernel memory boundary; validate fault handling and access checks before translating the pattern.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.