arch/mips/lantiq/prom.c

Source file repositories/reference/linux-study-clean/arch/mips/lantiq/prom.c

File Facts

System
Linux kernel
Corpus path
arch/mips/lantiq/prom.c
Extension
.c
Size
2557 bytes
Lines
117
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

if (CPHYSADDR(p) && *p) {
			strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
			strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
		}
	}
}

void __init plat_mem_setup(void)
{
	void *dtb;

	ioport_resource.start = IOPORT_RESOURCE_START;
	ioport_resource.end = IOPORT_RESOURCE_END;
	iomem_resource.start = IOMEM_RESOURCE_START;
	iomem_resource.end = IOMEM_RESOURCE_END;

	set_io_port_base((unsigned long) KSEG1);

	dtb = get_fdt();
	if (dtb == NULL)
		panic("no dtb found");

	/*
	 * Load the devicetree. This causes the chosen node to be
	 * parsed resulting in our memory appearing
	 */
	__dt_setup_arch(dtb);
}

#if defined(CONFIG_MIPS_MT_SMP)
static void lantiq_init_secondary(void)
{
	/*
	 * MIPS CPU startup function vsmp_init_secondary() will only
	 * enable some of the interrupts for the second CPU/VPE.
	 */
	set_c0_status(ST0_IM);
}
#endif

void __init prom_init(void)
{
	/* call the soc specific detetcion code and get it to fill soc_info */
	ltq_soc_detect(&soc_info);
	snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s",
		soc_info.name, soc_info.rev_type);
	soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
	pr_info("SoC: %s\n", soc_info.sys_type);
	prom_init_cmdline();

#if defined(CONFIG_MIPS_MT_SMP)
	lantiq_smp_ops = vsmp_smp_ops;
	if (cpu_has_mipsmt)
		lantiq_smp_ops.init_secondary = lantiq_init_secondary;
	register_smp_ops(&lantiq_smp_ops);
#endif
}

Annotation

Implementation Notes