arch/mips/lantiq/xway/clk.c
Source file repositories/reference/linux-study-clean/arch/mips/lantiq/xway/clk.c
File Facts
- System
- Linux kernel
- Corpus path
arch/mips/lantiq/xway/clk.c- Extension
.c- Size
- 5357 bytes
- Lines
- 352
- Domain
- Architecture Layer
- Bucket
- arch/mips
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
linux/io.hlinux/export.hlinux/clk.hasm/time.hasm/irq.hasm/div64.hlantiq_soc.h../clk.h
Detected Declarations
function ltq_danube_fpi_hzfunction ltq_danube_cpu_hzfunction ltq_danube_pp32_hzfunction ltq_ar9_sys_hzfunction ltq_ar9_fpi_hzfunction ltq_ar9_cpu_hzfunction ltq_vr9_cpu_hzfunction ltq_vr9_fpi_hzfunction ltq_vr9_pp32_hzfunction ltq_ar10_cpu_hzfunction ltq_ar10_fpi_hzfunction ltq_ar10_pp32_hzfunction ltq_grx390_cpu_hzfunction ltq_grx390_fpi_hzfunction ltq_grx390_pp32_hz
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only
/*
*
* Copyright (C) 2010 John Crispin <john@phrozen.org>
* Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
*/
#include <linux/io.h>
#include <linux/export.h>
#include <linux/clk.h>
#include <asm/time.h>
#include <asm/irq.h>
#include <asm/div64.h>
#include <lantiq_soc.h>
#include "../clk.h"
static unsigned int ram_clocks[] = {
CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
#define DDR_HZ ram_clocks[ltq_cgu_r32(CGU_SYS) & 0x3]
/* legacy xway clock */
#define CGU_SYS 0x10
/* vr9, ar10/grx390 clock */
#define CGU_SYS_XRX 0x0c
#define CGU_IF_CLK_AR10 0x24
unsigned long ltq_danube_fpi_hz(void)
{
unsigned long ddr_clock = DDR_HZ;
if (ltq_cgu_r32(CGU_SYS) & 0x40)
return ddr_clock >> 1;
return ddr_clock;
}
unsigned long ltq_danube_cpu_hz(void)
{
switch (ltq_cgu_r32(CGU_SYS) & 0xc) {
case 0:
return CLOCK_333M;
case 4:
return DDR_HZ;
case 8:
return DDR_HZ << 1;
default:
return DDR_HZ >> 1;
}
}
unsigned long ltq_danube_pp32_hz(void)
{
unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 7) & 3;
unsigned long clk;
switch (clksys) {
case 1:
clk = CLOCK_240M;
break;
case 2:
clk = CLOCK_222M;
break;
case 3:
clk = CLOCK_133M;
break;
default:
clk = CLOCK_266M;
break;
}
return clk;
}
static unsigned long ltq_ar9_sys_hz(void)
{
if (((ltq_cgu_r32(CGU_SYS) >> 3) & 0x3) == 0x2)
return CLOCK_393M;
return CLOCK_333M;
}
unsigned long ltq_ar9_fpi_hz(void)
{
unsigned long sys = ltq_ar9_sys_hz();
if (ltq_cgu_r32(CGU_SYS) & BIT(0))
return sys / 3;
else
Annotation
- Immediate include surface: `linux/io.h`, `linux/export.h`, `linux/clk.h`, `asm/time.h`, `asm/irq.h`, `asm/div64.h`, `lantiq_soc.h`, `../clk.h`.
- Detected declarations: `function ltq_danube_fpi_hz`, `function ltq_danube_cpu_hz`, `function ltq_danube_pp32_hz`, `function ltq_ar9_sys_hz`, `function ltq_ar9_fpi_hz`, `function ltq_ar9_cpu_hz`, `function ltq_vr9_cpu_hz`, `function ltq_vr9_fpi_hz`, `function ltq_vr9_pp32_hz`, `function ltq_ar10_cpu_hz`.
- Atlas domain: Architecture Layer / arch/mips.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.