arch/mips/loongson2ef/fuloong-2e/irq.c
Source file repositories/reference/linux-study-clean/arch/mips/loongson2ef/fuloong-2e/irq.c
File Facts
- System
- Linux kernel
- Corpus path
arch/mips/loongson2ef/fuloong-2e/irq.c- Extension
.c- Size
- 1555 bytes
- Lines
- 66
- Domain
- Architecture Layer
- Bucket
- arch/mips
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
linux/interrupt.hasm/irq_cpu.hasm/i8259.hloongson.h
Detected Declarations
function Copyrightfunction mach_irq_dispatchfunction mach_init_irq
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2007 Lemote Inc. & Institute of Computing Technology
* Author: Fuxin Zhang, zhangfx@lemote.com
*/
#include <linux/interrupt.h>
#include <asm/irq_cpu.h>
#include <asm/i8259.h>
#include <loongson.h>
static void i8259_irqdispatch(void)
{
int irq;
irq = i8259_irq();
if (irq >= 0)
do_IRQ(irq);
else
spurious_interrupt();
}
asmlinkage void mach_irq_dispatch(unsigned int pending)
{
if (pending & CAUSEF_IP7)
do_IRQ(MIPS_CPU_IRQ_BASE + 7);
else if (pending & CAUSEF_IP6) /* perf counter loverflow */
return;
else if (pending & CAUSEF_IP5)
i8259_irqdispatch();
else if (pending & CAUSEF_IP2)
bonito_irqdispatch();
else
spurious_interrupt();
}
void __init mach_init_irq(void)
{
int irq;
/* init all controller
* 0-15 ------> i8259 interrupt
* 16-23 ------> mips cpu interrupt
* 32-63 ------> bonito irq
*/
/* most bonito irq should be level triggered */
LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
/* Sets the first-level interrupt dispatcher. */
mips_cpu_irq_init();
init_i8259_irqs();
bonito_irq_init();
/* bonito irq at IP2 */
irq = MIPS_CPU_IRQ_BASE + 2;
if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade", NULL))
pr_err("Failed to request irq %d (cascade)\n", irq);
/* 8259 irq at IP5 */
irq = MIPS_CPU_IRQ_BASE + 5;
if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade", NULL))
pr_err("Failed to request irq %d (cascade)\n", irq);
}
Annotation
- Immediate include surface: `linux/interrupt.h`, `asm/irq_cpu.h`, `asm/i8259.h`, `loongson.h`.
- Detected declarations: `function Copyright`, `function mach_irq_dispatch`, `function mach_init_irq`.
- Atlas domain: Architecture Layer / arch/mips.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.