arch/mips/mm/c-r4k.c
Source file repositories/reference/linux-study-clean/arch/mips/mm/c-r4k.c
File Facts
- System
- Linux kernel
- Corpus path
arch/mips/mm/c-r4k.c- Extension
.c- Size
- 48236 bytes
- Lines
- 1827
- Domain
- Architecture Layer
- Bucket
- arch/mips
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/cpu_pm.hlinux/hardirq.hlinux/init.hlinux/highmem.hlinux/kernel.hlinux/linkage.hlinux/preempt.hlinux/sched.hlinux/smp.hlinux/mm.hlinux/export.hlinux/bitops.hlinux/dma-map-ops.hasm/bcache.hasm/bootinfo.hasm/cache.hasm/cacheops.hasm/cpu.hasm/cpu-features.hasm/cpu-type.hasm/io.hasm/page.hasm/r4kcache.hasm/sections.hasm/mmu_context.hasm/cacheflush.hasm/traps.hasm/mips-cps.h
Detected Declarations
struct flush_cache_page_argsstruct flush_icache_range_argsstruct flush_kernel_vmap_range_argsfunction Copyrightfunction r4k_on_each_cpufunction r4k_blast_dcache_page_dc32function r4k_blast_dcache_page_dc64function r4k_blast_dcache_page_dc128function r4k_blast_dcache_page_setupfunction r4k_blast_dcache_user_page_setupfunction r4k_blast_dcache_setupfunction __volatile__function tx49_blast_icache32function r4k_blast_icache_page_setupfunction r4k_blast_icache_user_page_setupfunction r4k_blast_icache_setupfunction r4k_blast_scache_page_setupfunction r4k_blast_scache_setupfunction r4k_blast_scache_node_setupfunction local_r4k___flush_cache_allfunction r4k___flush_cache_allfunction has_valid_asidfunction r4k__flush_cache_vmapfunction r4k__flush_cache_vunmapfunction local_r4k_flush_cache_rangefunction r4k_flush_cache_rangefunction local_r4k_flush_cache_mmfunction current_cpu_typefunction r4k_flush_cache_mmfunction local_r4k_flush_cache_pagefunction r4k_flush_cache_pagefunction local_r4k_flush_data_cache_pagefunction r4k_flush_data_cache_pagefunction __local_r4k_flush_icache_rangefunction local_r4k_flush_icache_rangefunction local_r4k_flush_icache_user_rangefunction local_r4k_flush_icache_range_ipifunction __r4k_flush_icache_rangefunction r4k_flush_icache_rangefunction r4k_flush_icache_user_rangefunction r4k_dma_cache_wback_invfunction prefetch_cache_invfunction r4k_dma_cache_invfunction r4k_flush_icache_allfunction local_r4k_flush_kernel_vmap_range_indexfunction local_r4k_flush_kernel_vmap_rangefunction r4k_flush_kernel_vmap_rangefunction rm7k_erratum31
Annotated Snippet
struct flush_cache_page_args {
struct vm_area_struct *vma;
unsigned long addr;
unsigned long pfn;
};
static inline void local_r4k_flush_cache_page(void *args)
{
struct flush_cache_page_args *fcp_args = args;
struct vm_area_struct *vma = fcp_args->vma;
unsigned long addr = fcp_args->addr;
struct page *page = pfn_to_page(fcp_args->pfn);
int exec = vma->vm_flags & VM_EXEC;
struct mm_struct *mm = vma->vm_mm;
int map_coherent = 0;
pmd_t *pmdp;
pte_t *ptep;
void *vaddr;
/*
* If owns no valid ASID yet, cannot possibly have gotten
* this page into the cache.
*/
if (!has_valid_asid(mm, R4K_HIT))
return;
addr &= PAGE_MASK;
pmdp = pmd_off(mm, addr);
ptep = pte_offset_kernel(pmdp, addr);
/*
* If the page isn't marked valid, the page cannot possibly be
* in the cache.
*/
if (!(pte_present(*ptep)))
return;
if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
vaddr = NULL;
else {
struct folio *folio = page_folio(page);
/*
* Use kmap_coherent or kmap_atomic to do flushes for
* another ASID than the current one.
*/
map_coherent = (cpu_has_dc_aliases &&
folio_mapped(folio) &&
!folio_test_dcache_dirty(folio));
if (map_coherent)
vaddr = kmap_coherent(page, addr);
else
vaddr = kmap_atomic(page);
addr = (unsigned long)vaddr;
}
if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
vaddr ? r4k_blast_dcache_page(addr) :
r4k_blast_dcache_user_page(addr);
if (exec && !cpu_icache_snoops_remote_store)
r4k_blast_scache_page(addr);
}
if (exec) {
if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
drop_mmu_context(mm);
} else
vaddr ? r4k_blast_icache_page(addr) :
r4k_blast_icache_user_page(addr);
}
if (vaddr) {
if (map_coherent)
kunmap_coherent();
else
kunmap_atomic(vaddr);
}
}
static void r4k_flush_cache_page(struct vm_area_struct *vma,
unsigned long addr, unsigned long pfn)
{
struct flush_cache_page_args args;
args.vma = vma;
args.addr = addr;
args.pfn = pfn;
r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_page, &args);
}
static inline void local_r4k_flush_data_cache_page(void * addr)
Annotation
- Immediate include surface: `linux/cpu_pm.h`, `linux/hardirq.h`, `linux/init.h`, `linux/highmem.h`, `linux/kernel.h`, `linux/linkage.h`, `linux/preempt.h`, `linux/sched.h`.
- Detected declarations: `struct flush_cache_page_args`, `struct flush_icache_range_args`, `struct flush_kernel_vmap_range_args`, `function Copyright`, `function r4k_on_each_cpu`, `function r4k_blast_dcache_page_dc32`, `function r4k_blast_dcache_page_dc64`, `function r4k_blast_dcache_page_dc128`, `function r4k_blast_dcache_page_setup`, `function r4k_blast_dcache_user_page_setup`.
- Atlas domain: Architecture Layer / arch/mips.
- Implementation status: integration implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.