arch/mips/mm/cex-sb1.S

Source file repositories/reference/linux-study-clean/arch/mips/mm/cex-sb1.S

File Facts

System
Linux kernel
Corpus path
arch/mips/mm/cex-sb1.S
Extension
.S
Size
3975 bytes
Lines
158
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: arch/mips
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/stackframe.h>
#include <asm/cacheops.h>
#include <asm/sibyte/board.h>

#define C0_ERRCTL     $26	      /* CP0: Error info */
#define C0_CERR_I     $27	      /* CP0: Icache error */
#define C0_CERR_D     $27,1	      /* CP0: Dcache error */

	/*
	 * Based on SiByte sample software cache-err/cerr.S
	 * CVS revision 1.8.  Only the 'unrecoverable' case
	 * is changed.
	 */

	.set	mips64
	.set	noreorder
	.set	noat

	/*
	 * sb1_cerr_vec: code to be copied to the Cache Error
	 * Exception vector.  The code must be pushed out to memory
	 * (either by copying to Kseg0 and Kseg1 both, or by flushing
	 * the L1 and L2) since it is fetched as 0xa0000100.
	 *
	 * NOTE: Be sure this handler is at most 28 instructions long
	 * since the final 16 bytes of the exception vector memory
	 * (0x170-0x17f) are used to preserve k0, k1, and ra.
	 */

LEAF(except_vec2_sb1)
	/*
	 * If this error is recoverable, we need to exit the handler
	 * without having dirtied any registers.  To do this,
	 * save/restore k0 and k1 from low memory (Useg is direct
	 * mapped while ERL=1). Note that we can't save to a
	 * CPU-specific location without ruining a register in the
	 * process.  This means we are vulnerable to data corruption
	 * whenever the handler is reentered by a second CPU.
	 */
	sd	k0,0x170($0)
	sd	k1,0x178($0)

#ifdef CONFIG_SB1_CEX_ALWAYS_FATAL
	j	handle_vec2_sb1
	 nop
#else
	/*
	 * M_ERRCTL_RECOVERABLE is bit 31, which makes it easy to tell
	 * if we can fast-path out of here for a h/w-recovered error.
	 */
	mfc0	k1,C0_ERRCTL
	bgtz	k1,attempt_recovery
	 sll	k0,k1,1

recovered_dcache:
	/*
	 * Unlock CacheErr-D (which in turn unlocks CacheErr-DPA).
	 * Ought to log the occurrence of this recovered dcache error.
	 */
	b	recovered
	 mtc0	$0,C0_CERR_D

attempt_recovery:
	/*
	 * k0 has C0_ERRCTL << 1, which puts 'DC' at bit 31.  Any
	 * Dcache errors we can recover from will take more extensive
	 * processing.	For now, they are considered "unrecoverable".

Annotation

Implementation Notes