arch/mips/mm/tlb-r4k.c
Source file repositories/reference/linux-study-clean/arch/mips/mm/tlb-r4k.c
File Facts
- System
- Linux kernel
- Corpus path
arch/mips/mm/tlb-r4k.c- Extension
.c- Size
- 21459 bytes
- Lines
- 863
- Domain
- Architecture Layer
- Bucket
- arch/mips
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/cpu_pm.hlinux/init.hlinux/sched.hlinux/smp.hlinux/memblock.hlinux/minmax.hlinux/mm.hlinux/hugetlb.hlinux/export.hlinux/sort.hasm/cpu.hasm/cpu-type.hasm/bootinfo.hasm/hazards.hasm/mmu_context.hasm/tlb.hasm/tlbdebug.hasm/tlbex.hasm/tlbmisc.hasm/setup.h
Detected Declarations
struct tlbentfunction Copyrightfunction flush_micro_tlb_vmfunction local_flush_tlb_allfunction local_flush_tlb_rangefunction local_flush_tlb_kernel_rangefunction local_flush_tlb_pagefunction local_flush_tlb_onefunction update_mmu_cachefunction add_wired_entryfunction has_transparent_hugepagefunction add_temporary_entryfunction set_ntlbfunction read_c0_entryhi_nativefunction write_c0_entryhi_nativefunction r4k_entry_cmpfunction r4k_tlb_uniquify_readfunction r4k_tlb_uniquify_writefunction r4k_tlb_uniquifyfunction TLBfunction tlb_initfunction r4k_tlb_pm_notifierfunction r4k_tlb_init_pmexport local_flush_tlb_allexport has_transparent_hugepage
Annotated Snippet
struct tlbent {
unsigned long long wired:1;
unsigned long long global:1;
unsigned long long asid:10;
unsigned long long vpn:51;
unsigned long long pagesz:5;
unsigned long long index:14;
};
/*
* Comparison function for TLB entry sorting. Place wired entries first,
* then global entries, then order by the increasing VPN/ASID and the
* decreasing page size. This lets us avoid clashes with wired entries
* easily and get entries for larger pages out of the way first.
*
* We could group bits so as to reduce the number of comparisons, but this
* is seldom executed and not performance-critical, so prefer legibility.
*/
static int r4k_entry_cmp(const void *a, const void *b)
{
struct tlbent ea = *(struct tlbent *)a, eb = *(struct tlbent *)b;
if (ea.wired > eb.wired)
return -1;
else if (ea.wired < eb.wired)
return 1;
else if (ea.global > eb.global)
return -1;
else if (ea.global < eb.global)
return 1;
else if (ea.vpn < eb.vpn)
return -1;
else if (ea.vpn > eb.vpn)
return 1;
else if (ea.asid < eb.asid)
return -1;
else if (ea.asid > eb.asid)
return 1;
else if (ea.pagesz > eb.pagesz)
return -1;
else if (ea.pagesz < eb.pagesz)
return 1;
else
return 0;
}
/*
* Fetch all the TLB entries. Mask individual VPN values retrieved with
* the corresponding page mask and ignoring any 1KiB extension as we'll
* be using 4KiB pages for uniquification.
*/
static void __ref r4k_tlb_uniquify_read(struct tlbent *tlb_vpns, int tlbsize)
{
int start = num_wired_entries();
unsigned long long vpn_mask;
bool global;
int i;
vpn_mask = GENMASK(current_cpu_data.vmbits - 1, VPN2_SHIFT);
vpn_mask |= cpu_has_64bits ? 3ULL << 62 : 1 << 31;
for (i = 0; i < tlbsize; i++) {
unsigned long long entryhi, vpn, mask, asid;
unsigned int pagesz;
write_c0_index(i);
mtc0_tlbr_hazard();
tlb_read();
tlb_read_hazard();
global = !!(read_c0_entrylo0() & ENTRYLO_G);
entryhi = read_c0_entryhi_native();
mask = read_c0_pagemask();
asid = entryhi & cpu_asid_mask(¤t_cpu_data);
vpn = (entryhi & vpn_mask & ~mask) >> VPN2_SHIFT;
pagesz = ilog2((mask >> VPN2_SHIFT) + 1);
tlb_vpns[i].global = global;
tlb_vpns[i].asid = global ? 0 : asid;
tlb_vpns[i].vpn = vpn;
tlb_vpns[i].pagesz = pagesz;
tlb_vpns[i].wired = i < start;
tlb_vpns[i].index = i;
}
}
/*
* Write unique values to all but the wired TLB entries each, using
* the 4KiB page size. This size might not be supported with R6, but
Annotation
- Immediate include surface: `linux/cpu_pm.h`, `linux/init.h`, `linux/sched.h`, `linux/smp.h`, `linux/memblock.h`, `linux/minmax.h`, `linux/mm.h`, `linux/hugetlb.h`.
- Detected declarations: `struct tlbent`, `function Copyright`, `function flush_micro_tlb_vm`, `function local_flush_tlb_all`, `function local_flush_tlb_range`, `function local_flush_tlb_kernel_range`, `function local_flush_tlb_page`, `function local_flush_tlb_one`, `function update_mmu_cache`, `function add_wired_entry`.
- Atlas domain: Architecture Layer / arch/mips.
- Implementation status: integration implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.