arch/mips/pci/pci-ar71xx.c
Source file repositories/reference/linux-study-clean/arch/mips/pci/pci-ar71xx.c
File Facts
- System
- Linux kernel
- Corpus path
arch/mips/pci/pci-ar71xx.c- Extension
.c- Size
- 9984 bytes
- Lines
- 402
- Domain
- Architecture Layer
- Bucket
- arch/mips
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/resource.hlinux/types.hlinux/delay.hlinux/bitops.hlinux/pci.hlinux/pci_regs.hlinux/interrupt.hlinux/init.hlinux/platform_device.hasm/mach-ath79/ar71xx_regs.hasm/mach-ath79/ath79.h
Detected Declarations
struct ar71xx_pci_controllerfunction ar71xx_pci_get_blefunction ar71xx_pci_bus_addrfunction pci_bus_to_ar71xx_controllerfunction ar71xx_pci_check_errorfunction ar71xx_pci_local_writefunction ar71xx_pci_set_cfgaddrfunction ar71xx_pci_read_configfunction ar71xx_pci_write_configfunction ar71xx_pci_irq_handlerfunction ar71xx_pci_irq_unmaskfunction ar71xx_pci_irq_maskfunction ar71xx_pci_irq_initfunction ar71xx_pci_resetfunction ar71xx_pci_probefunction ar71xx_pci_init
Annotated Snippet
struct ar71xx_pci_controller {
void __iomem *cfg_base;
int irq;
int irq_base;
struct pci_controller pci_ctrl;
struct resource io_res;
struct resource mem_res;
};
/* Byte lane enable bits */
static const u8 ar71xx_pci_ble_table[4][4] = {
{0x0, 0xf, 0xf, 0xf},
{0xe, 0xd, 0xb, 0x7},
{0xc, 0xf, 0x3, 0xf},
{0xf, 0xf, 0xf, 0xf},
};
static const u32 ar71xx_pci_read_mask[8] = {
0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0
};
static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
{
u32 t;
t = ar71xx_pci_ble_table[size & 3][where & 3];
BUG_ON(t == 0xf);
t <<= (local) ? 20 : 4;
return t;
}
static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
int where)
{
u32 ret;
if (!bus->number) {
/* type 0 */
ret = (1 << PCI_SLOT(devfn)) | (PCI_FUNC(devfn) << 8) |
(where & ~3);
} else {
/* type 1 */
ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11) |
(PCI_FUNC(devfn) << 8) | (where & ~3) | 1;
}
return ret;
}
static inline struct ar71xx_pci_controller *
pci_bus_to_ar71xx_controller(struct pci_bus *bus)
{
struct pci_controller *hose;
hose = (struct pci_controller *) bus->sysdata;
return container_of(hose, struct ar71xx_pci_controller, pci_ctrl);
}
static int ar71xx_pci_check_error(struct ar71xx_pci_controller *apc, int quiet)
{
void __iomem *base = apc->cfg_base;
u32 pci_err;
u32 ahb_err;
pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3;
if (pci_err) {
if (!quiet) {
u32 addr;
addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR);
pr_crit("ar71xx: %s bus error %d at addr 0x%x\n",
"PCI", pci_err, addr);
}
/* clear PCI error status */
__raw_writel(pci_err, base + AR71XX_PCI_REG_PCI_ERR);
}
ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1;
if (ahb_err) {
if (!quiet) {
u32 addr;
addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR);
pr_crit("ar71xx: %s bus error %d at addr 0x%x\n",
"AHB", ahb_err, addr);
}
/* clear AHB error status */
Annotation
- Immediate include surface: `linux/resource.h`, `linux/types.h`, `linux/delay.h`, `linux/bitops.h`, `linux/pci.h`, `linux/pci_regs.h`, `linux/interrupt.h`, `linux/init.h`.
- Detected declarations: `struct ar71xx_pci_controller`, `function ar71xx_pci_get_ble`, `function ar71xx_pci_bus_addr`, `function pci_bus_to_ar71xx_controller`, `function ar71xx_pci_check_error`, `function ar71xx_pci_local_write`, `function ar71xx_pci_set_cfgaddr`, `function ar71xx_pci_read_config`, `function ar71xx_pci_write_config`, `function ar71xx_pci_irq_handler`.
- Atlas domain: Architecture Layer / arch/mips.
- Implementation status: integration implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.