arch/mips/pci/pci-rc32434.c

Source file repositories/reference/linux-study-clean/arch/mips/pci/pci-rc32434.c

File Facts

System
Linux kernel
Corpus path
arch/mips/pci/pci-rc32434.c
Extension
.c
Size
7447 bytes
Lines
232
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>

#include <asm/mach-rc32434/rc32434.h>
#include <asm/mach-rc32434/pci.h>

#define PCI_ACCESS_READ	 0
#define PCI_ACCESS_WRITE 1

/* define an unsigned array for the PCI registers */
static unsigned int korina_cnfg_regs[25] = {
	KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4,
	KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8,
	KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
	KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
	KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
	KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
};
static struct resource rc32434_res_pci_mem1;
static struct resource rc32434_res_pci_mem2;

static struct resource rc32434_res_pci_mem1 = {
	.name = "PCI MEM1",
	.start = 0x50000000,
	.end = 0x5FFFFFFF,
	.flags = IORESOURCE_MEM,
	.sibling = NULL,
	.child = &rc32434_res_pci_mem2
};

static struct resource rc32434_res_pci_mem2 = {
	.name = "PCI Mem2",
	.start = 0x60000000,
	.end = 0x6FFFFFFF,
	.flags = IORESOURCE_MEM,
	.parent = &rc32434_res_pci_mem1,
	.sibling = NULL,
	.child = NULL
};

static struct resource rc32434_res_pci_io1 = {
	.name = "PCI I/O1",
	.start = 0x18800000,
	.end = 0x188FFFFF,
	.flags = IORESOURCE_IO,
};

extern struct pci_ops rc32434_pci_ops;

#define PCI_MEM1_START	PCI_ADDR_START
#define PCI_MEM1_END	(PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1)
#define PCI_MEM2_START	(PCI_ADDR_START + CPUTOPCI_MEM_WIN)
#define PCI_MEM2_END	(PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN)  - 1)
#define PCI_IO1_START	(PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN))
#define PCI_IO1_END							\
	(PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN - 1)
#define PCI_IO2_START							\
	(PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN)
#define PCI_IO2_END							\
	(PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) - 1)

struct pci_controller rc32434_controller2;

struct pci_controller rc32434_controller = {
	.pci_ops = &rc32434_pci_ops,
	.mem_resource = &rc32434_res_pci_mem1,
	.io_resource = &rc32434_res_pci_io1,
	.mem_offset = 0,
	.io_offset = 0,

};

#ifdef __MIPSEB__
#define PCI_ENDIAN_FLAG PCILBAC_sb_m
#else
#define PCI_ENDIAN_FLAG 0
#endif

static int __init rc32434_pcibridge_init(void)
{
	unsigned int pcicvalue, pcicdata = 0;
	unsigned int dummyread, pcicntlval;
	int loopCount;
	unsigned int pci_config_addr;

	pcicvalue = rc32434_pci->pcic;
	pcicvalue = (pcicvalue >> PCIM_SHFT) & PCIM_BIT_LEN;
	if (!((pcicvalue == PCIM_H_EA) ||

Annotation

Implementation Notes