arch/mips/sgi-ip32/crime.c
Source file repositories/reference/linux-study-clean/arch/mips/sgi-ip32/crime.c
File Facts
- System
- Linux kernel
- Corpus path
arch/mips/sgi-ip32/crime.c- Extension
.c- Size
- 2841 bytes
- Lines
- 106
- Domain
- Architecture Layer
- Bucket
- arch/mips
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/types.hlinux/init.hlinux/kernel.hlinux/interrupt.hlinux/export.hasm/bootinfo.hasm/io.hasm/mipsregs.hasm/page.hasm/ip32/crime.hasm/ip32/mace.hip32-common.h
Detected Declarations
function crime_initfunction crime_memerr_intrfunction crime_cpuerr_intrexport mace
Annotated Snippet
#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/export.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/mipsregs.h>
#include <asm/page.h>
#include <asm/ip32/crime.h>
#include <asm/ip32/mace.h>
#include "ip32-common.h"
struct sgi_crime __iomem *crime;
struct sgi_mace __iomem *mace;
EXPORT_SYMBOL_GPL(mace);
void __init crime_init(void)
{
unsigned int id, rev;
const int field = 2 * sizeof(unsigned long);
set_io_port_base((unsigned long) ioremap(MACEPCI_LOW_IO, 0x2000000));
crime = ioremap(CRIME_BASE, sizeof(struct sgi_crime));
mace = ioremap(MACE_BASE, sizeof(struct sgi_mace));
id = crime->id;
rev = id & CRIME_ID_REV;
id = (id & CRIME_ID_IDBITS) >> 4;
printk(KERN_INFO "CRIME id %1x rev %d at 0x%0*lx\n",
id, rev, field, (unsigned long) CRIME_BASE);
}
irqreturn_t crime_memerr_intr(int irq, void *dev_id)
{
unsigned long stat, addr;
int fatal = 0;
stat = crime->mem_error_stat & CRIME_MEM_ERROR_STAT_MASK;
addr = crime->mem_error_addr & CRIME_MEM_ERROR_ADDR_MASK;
printk("CRIME memory error at 0x%08lx ST 0x%08lx<", addr, stat);
if (stat & CRIME_MEM_ERROR_INV)
printk("INV,");
if (stat & CRIME_MEM_ERROR_ECC) {
unsigned long ecc_syn =
crime->mem_ecc_syn & CRIME_MEM_ERROR_ECC_SYN_MASK;
unsigned long ecc_gen =
crime->mem_ecc_chk & CRIME_MEM_ERROR_ECC_CHK_MASK;
printk("ECC,SYN=0x%08lx,GEN=0x%08lx,", ecc_syn, ecc_gen);
}
if (stat & CRIME_MEM_ERROR_MULTIPLE) {
fatal = 1;
printk("MULTIPLE,");
}
if (stat & CRIME_MEM_ERROR_HARD_ERR) {
fatal = 1;
printk("HARD,");
}
if (stat & CRIME_MEM_ERROR_SOFT_ERR)
printk("SOFT,");
if (stat & CRIME_MEM_ERROR_CPU_ACCESS)
printk("CPU,");
if (stat & CRIME_MEM_ERROR_VICE_ACCESS)
printk("VICE,");
if (stat & CRIME_MEM_ERROR_GBE_ACCESS)
printk("GBE,");
if (stat & CRIME_MEM_ERROR_RE_ACCESS)
printk("RE,REID=0x%02lx,", (stat & CRIME_MEM_ERROR_RE_ID)>>8);
if (stat & CRIME_MEM_ERROR_MACE_ACCESS)
printk("MACE,MACEID=0x%02lx,", stat & CRIME_MEM_ERROR_MACE_ID);
crime->mem_error_stat = 0;
if (fatal) {
printk("FATAL>\n");
panic("Fatal memory error.");
} else
printk("NONFATAL>\n");
return IRQ_HANDLED;
}
irqreturn_t crime_cpuerr_intr(int irq, void *dev_id)
{
unsigned long stat = crime->cpu_error_stat & CRIME_CPU_ERROR_MASK;
unsigned long addr = crime->cpu_error_addr & CRIME_CPU_ERROR_ADDR_MASK;
Annotation
- Immediate include surface: `linux/types.h`, `linux/init.h`, `linux/kernel.h`, `linux/interrupt.h`, `linux/export.h`, `asm/bootinfo.h`, `asm/io.h`, `asm/mipsregs.h`.
- Detected declarations: `function crime_init`, `function crime_memerr_intr`, `function crime_cpuerr_intr`, `export mace`.
- Atlas domain: Architecture Layer / arch/mips.
- Implementation status: integration implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.