arch/mips/sibyte/swarm/rtc_m41t81.c

Source file repositories/reference/linux-study-clean/arch/mips/sibyte/swarm/rtc_m41t81.c

File Facts

System
Linux kernel
Corpus path
arch/mips/sibyte/swarm/rtc_m41t81.c
Extension
.c
Size
6711 bytes
Lines
229
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2000, 2001 Broadcom Corporation
 *
 * Copyright (C) 2002 MontaVista Software Inc.
 * Author: jsun@mvista.com or jsun@junsun.net
 */
#include <linux/bcd.h>
#include <linux/types.h>
#include <linux/time.h>

#include <asm/time.h>
#include <asm/addrspace.h>
#include <asm/io.h>

#include <asm/sibyte/sb1250.h>
#include <asm/sibyte/sb1250_regs.h>
#include <asm/sibyte/sb1250_smbus.h>


/* M41T81 definitions */

/*
 * Register bits
 */

#define M41T81REG_SC_ST		0x80		/* stop bit */
#define M41T81REG_HR_CB		0x40		/* century bit */
#define M41T81REG_HR_CEB	0x80		/* century enable bit */
#define M41T81REG_CTL_S		0x20		/* sign bit */
#define M41T81REG_CTL_FT	0x40		/* frequency test bit */
#define M41T81REG_CTL_OUT	0x80		/* output level */
#define M41T81REG_WD_RB0	0x01		/* watchdog resolution bit 0 */
#define M41T81REG_WD_RB1	0x02		/* watchdog resolution bit 1 */
#define M41T81REG_WD_BMB0	0x04		/* watchdog multiplier bit 0 */
#define M41T81REG_WD_BMB1	0x08		/* watchdog multiplier bit 1 */
#define M41T81REG_WD_BMB2	0x10		/* watchdog multiplier bit 2 */
#define M41T81REG_WD_BMB3	0x20		/* watchdog multiplier bit 3 */
#define M41T81REG_WD_BMB4	0x40		/* watchdog multiplier bit 4 */
#define M41T81REG_AMO_ABE	0x20		/* alarm in "battery back-up mode" enable bit */
#define M41T81REG_AMO_SQWE	0x40		/* square wave enable */
#define M41T81REG_AMO_AFE	0x80		/* alarm flag enable flag */
#define M41T81REG_ADT_RPT5	0x40		/* alarm repeat mode bit 5 */
#define M41T81REG_ADT_RPT4	0x80		/* alarm repeat mode bit 4 */
#define M41T81REG_AHR_RPT3	0x80		/* alarm repeat mode bit 3 */
#define M41T81REG_AHR_HT	0x40		/* halt update bit */
#define M41T81REG_AMN_RPT2	0x80		/* alarm repeat mode bit 2 */
#define M41T81REG_ASC_RPT1	0x80		/* alarm repeat mode bit 1 */
#define M41T81REG_FLG_AF	0x40		/* alarm flag (read only) */
#define M41T81REG_FLG_WDF	0x80		/* watchdog flag (read only) */
#define M41T81REG_SQW_RS0	0x10		/* sqw frequency bit 0 */
#define M41T81REG_SQW_RS1	0x20		/* sqw frequency bit 1 */
#define M41T81REG_SQW_RS2	0x40		/* sqw frequency bit 2 */
#define M41T81REG_SQW_RS3	0x80		/* sqw frequency bit 3 */


/*
 * Register numbers
 */

#define M41T81REG_TSC	0x00		/* tenths/hundredths of second */
#define M41T81REG_SC	0x01		/* seconds */
#define M41T81REG_MN	0x02		/* minute */
#define M41T81REG_HR	0x03		/* hour/century */
#define M41T81REG_DY	0x04		/* day of week */
#define M41T81REG_DT	0x05		/* date of month */
#define M41T81REG_MO	0x06		/* month */
#define M41T81REG_YR	0x07		/* year */
#define M41T81REG_CTL	0x08		/* control */
#define M41T81REG_WD	0x09		/* watchdog */
#define M41T81REG_AMO	0x0A		/* alarm: month */
#define M41T81REG_ADT	0x0B		/* alarm: date */
#define M41T81REG_AHR	0x0C		/* alarm: hour */
#define M41T81REG_AMN	0x0D		/* alarm: minute */
#define M41T81REG_ASC	0x0E		/* alarm: second */
#define M41T81REG_FLG	0x0F		/* flags */
#define M41T81REG_SQW	0x13		/* square wave register */

#define M41T81_CCR_ADDRESS	0x68

#define SMB_CSR(reg)	IOADDR(A_SMB_REGISTER(1, reg))

static int m41t81_read(uint8_t addr)
{
	while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
		;

	__raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD));
	__raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE,
		     SMB_CSR(R_SMB_START));

Annotation

Implementation Notes