arch/mips/txx9/rbtx4927/setup.c

Source file repositories/reference/linux-study-clean/arch/mips/txx9/rbtx4927/setup.c

File Facts

System
Linux kernel
Corpus path
arch/mips/txx9/rbtx4927/setup.c
Extension
.c
Size
10753 bytes
Lines
381
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

txx9_pci66_check(c, 0, 0)) {
		/* Reset PCI Bus */
		writeb(1, rbtx4927_pcireset_addr);
		/* Reset PCIC */
		txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
		tx4927_pciclk66_setup();
		mdelay(10);
		/* clear PCIC reset */
		txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
		writeb(0, rbtx4927_pcireset_addr);
		iob();
		/* Reinitialize PCIC */
		tx4927_report_pciclk();
		tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
	}
	tx4927_setup_pcierr_irq();
}

static void __init tx4937_pci_setup(void)
{
	int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
	struct pci_controller *c = &txx9_primary_pcic;

	register_pci_controller(c);

	if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
		txx9_pci_option =
			(txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
			TXX9_PCI_OPT_CLK_66; /* already configured */

	/* Reset PCI Bus */
	writeb(1, rbtx4927_pcireset_addr);
	/* Reset PCIC */
	txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
	    TXX9_PCI_OPT_CLK_66)
		tx4938_pciclk66_setup();
	mdelay(10);
	/* clear PCIC reset */
	txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
	writeb(0, rbtx4927_pcireset_addr);
	iob();

	tx4938_report_pciclk();
	tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
	    TXX9_PCI_OPT_CLK_AUTO &&
	    txx9_pci66_check(c, 0, 0)) {
		/* Reset PCI Bus */
		writeb(1, rbtx4927_pcireset_addr);
		/* Reset PCIC */
		txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
		tx4938_pciclk66_setup();
		mdelay(10);
		/* clear PCIC reset */
		txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
		writeb(0, rbtx4927_pcireset_addr);
		iob();
		/* Reinitialize PCIC */
		tx4938_report_pciclk();
		tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
	}
	tx4938_setup_pcierr_irq();
}
#else
static inline void tx4927_pci_setup(void) {}
static inline void tx4937_pci_setup(void) {}
#endif /* CONFIG_PCI */

static void __init rbtx4927_gpio_init(void)
{
	/* TX4927-SIO DTR on (PIO[15]) */
	gpio_request(15, "sio-dtr");
	gpio_direction_output(15, 1);

	tx4927_sio_init(0, 0);
}

static void __init rbtx4927_arch_init(void)
{
	txx9_gpio_init(TX4927_PIO_REG & 0xfffffffffULL, 0, TX4927_NUM_PIO);

	rbtx4927_gpio_init();

	tx4927_pci_setup();
}

static void __init rbtx4937_arch_init(void)
{
	txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO);

Annotation

Implementation Notes