arch/nios2/mm/mmu_context.c
Source file repositories/reference/linux-study-clean/arch/nios2/mm/mmu_context.c
File Facts
- System
- Linux kernel
- Corpus path
arch/nios2/mm/mmu_context.c- Extension
.c- Size
- 3102 bytes
- Lines
- 117
- Domain
- Architecture Layer
- Bucket
- arch/nios2
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/mm.hasm/cpuinfo.hasm/mmu_context.hasm/tlb.h
Detected Declarations
function mmu_context_initfunction contextfunction get_new_contextfunction switch_mmfunction activate_mmfunction get_pid_from_context
Annotated Snippet
#include <linux/mm.h>
#include <asm/cpuinfo.h>
#include <asm/mmu_context.h>
#include <asm/tlb.h>
/* The pids position and mask in context */
#define PID_SHIFT 0
#define PID_BITS (cpuinfo.tlb_pid_num_bits)
#define PID_MASK ((1UL << PID_BITS) - 1)
/* The versions position and mask in context */
#define VERSION_BITS (32 - PID_BITS)
#define VERSION_SHIFT (PID_SHIFT + PID_BITS)
#define VERSION_MASK ((1UL << VERSION_BITS) - 1)
/* Return the version part of a context */
#define CTX_VERSION(c) (((c) >> VERSION_SHIFT) & VERSION_MASK)
/* Return the pid part of a context */
#define CTX_PID(c) (((c) >> PID_SHIFT) & PID_MASK)
/* Value of the first context (version 1, pid 0) */
#define FIRST_CTX ((1UL << VERSION_SHIFT) | (0 << PID_SHIFT))
static mm_context_t next_mmu_context;
/*
* Initialize MMU context management stuff.
*/
void __init mmu_context_init(void)
{
/* We need to set this here because the value depends on runtime data
* from cpuinfo */
next_mmu_context = FIRST_CTX;
}
/*
* Set new context (pid), keep way
*/
static void set_context(mm_context_t context)
{
set_mmu_pid(CTX_PID(context));
}
static mm_context_t get_new_context(void)
{
/* Return the next pid */
next_mmu_context += (1UL << PID_SHIFT);
/* If the pid field wraps around we increase the version and
* flush the tlb */
if (unlikely(CTX_PID(next_mmu_context) == 0)) {
/* Version is incremented since the pid increment above
* overflows info version */
flush_cache_all();
flush_tlb_all();
}
/* If the version wraps we start over with the first generation, we do
* not need to flush the tlb here since it's always done above */
if (unlikely(CTX_VERSION(next_mmu_context) == 0))
next_mmu_context = FIRST_CTX;
return next_mmu_context;
}
void switch_mm(struct mm_struct *prev, struct mm_struct *next,
struct task_struct *tsk)
{
unsigned long flags;
local_irq_save(flags);
/* If the process context we are swapping in has a different context
* generation then we have it should get a new generation/pid */
if (unlikely(CTX_VERSION(next->context) !=
CTX_VERSION(next_mmu_context)))
next->context = get_new_context();
/* Save the current pgd so the fast tlb handler can find it */
pgd_current = next->pgd;
/* Set the current context */
set_context(next->context);
local_irq_restore(flags);
}
/*
Annotation
- Immediate include surface: `linux/mm.h`, `asm/cpuinfo.h`, `asm/mmu_context.h`, `asm/tlb.h`.
- Detected declarations: `function mmu_context_init`, `function context`, `function get_new_context`, `function switch_mm`, `function activate_mm`, `function get_pid_from_context`.
- Atlas domain: Architecture Layer / arch/nios2.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.