arch/openrisc/include/asm/uaccess.h
Source file repositories/reference/linux-study-clean/arch/openrisc/include/asm/uaccess.h
File Facts
- System
- Linux kernel
- Corpus path
arch/openrisc/include/asm/uaccess.h- Extension
.h- Size
- 6825 bytes
- Lines
- 238
- Domain
- Architecture Layer
- Bucket
- arch/openrisc
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Touches user memory; correctness depends on fault-safe copying and privilege boundary handling.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/prefetch.hlinux/string.hasm/page.hasm/extable.hasm-generic/access_ok.h
Detected Declarations
struct __large_structfunction raw_copy_from_userfunction raw_copy_to_userfunction clear_user
Annotated Snippet
struct __large_struct {
unsigned long buf[100];
};
#define __m(x) (*(struct __large_struct *)(x))
/*
* We don't tell gcc that we are accessing memory, but this is OK
* because we do not write to any memory gcc knows about, so there
* are no aliasing issues.
*/
#define __put_user_asm(x, addr, err, op) \
__asm__ __volatile__( \
"1: "op" 0(%2),%1\n" \
"2:\n" \
".section .fixup,\"ax\"\n" \
"3: l.addi %0,r0,%3\n" \
" l.j 2b\n" \
" l.nop\n" \
".previous\n" \
".section __ex_table,\"a\"\n" \
" .align 2\n" \
" .long 1b,3b\n" \
".previous" \
: "=r"(err) \
: "r"(x), "r"(addr), "i"(-EFAULT), "0"(err))
#define __put_user_asm2(x, addr, err) \
__asm__ __volatile__( \
"1: l.sw 0(%2),%1\n" \
"2: l.sw 4(%2),%H1\n" \
"3:\n" \
".section .fixup,\"ax\"\n" \
"4: l.addi %0,r0,%3\n" \
" l.j 3b\n" \
" l.nop\n" \
".previous\n" \
".section __ex_table,\"a\"\n" \
" .align 2\n" \
" .long 1b,4b\n" \
" .long 2b,4b\n" \
".previous" \
: "=r"(err) \
: "r"(x), "r"(addr), "i"(-EFAULT), "0"(err))
#define __get_user_nocheck(x, ptr, size) \
({ \
long __gu_err; \
__get_user_size((x), (ptr), (size), __gu_err); \
__gu_err; \
})
#define __get_user_check(x, ptr, size) \
({ \
long __gu_err = -EFAULT; \
const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \
if (access_ok(__gu_addr, size)) \
__get_user_size((x), __gu_addr, (size), __gu_err); \
else \
(x) = (__typeof__(*(ptr))) 0; \
__gu_err; \
})
extern long __get_user_bad(void);
#define __get_user_size(x, ptr, size, retval) \
do { \
retval = 0; \
switch (size) { \
case 1: __get_user_asm(x, ptr, retval, "l.lbz"); break; \
case 2: __get_user_asm(x, ptr, retval, "l.lhz"); break; \
case 4: __get_user_asm(x, ptr, retval, "l.lwz"); break; \
case 8: __get_user_asm2(x, ptr, retval); break; \
default: (x) = (__typeof__(*(ptr)))__get_user_bad(); \
} \
} while (0)
#define __get_user_asm(x, addr, err, op) \
{ \
unsigned long __gu_tmp; \
__asm__ __volatile__( \
"1: "op" %1,0(%2)\n" \
"2:\n" \
".section .fixup,\"ax\"\n" \
"3: l.addi %0,r0,%3\n" \
" l.addi %1,r0,0\n" \
" l.j 2b\n" \
" l.nop\n" \
".previous\n" \
".section __ex_table,\"a\"\n" \
" .align 2\n" \
Annotation
- Immediate include surface: `linux/prefetch.h`, `linux/string.h`, `asm/page.h`, `asm/extable.h`, `asm-generic/access_ok.h`.
- Detected declarations: `struct __large_struct`, `function raw_copy_from_user`, `function raw_copy_to_user`, `function clear_user`.
- Atlas domain: Architecture Layer / arch/openrisc.
- Implementation status: source implementation candidate.
- This snippet crosses the user/kernel memory boundary; validate fault handling and access checks before translating the pattern.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.