arch/powerpc/boot/dcr.h

Source file repositories/reference/linux-study-clean/arch/powerpc/boot/dcr.h

File Facts

System
Linux kernel
Corpus path
arch/powerpc/boot/dcr.h
Extension
.h
Size
6237 bytes
Lines
198
Domain
Architecture Layer
Bucket
arch/powerpc
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _PPC_BOOT_DCR_H_
#define _PPC_BOOT_DCR_H_

#define mfdcr(rn) \
	({	\
		unsigned long rval; \
		asm volatile("mfdcr %0,%1" : "=r"(rval) : "i"(rn)); \
		rval; \
	})
#define mtdcr(rn, val) \
	asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val))
#define mfdcrx(rn) \
	({	\
		unsigned long rval; \
		asm volatile("mfdcrx %0,%1" : "=r"(rval) : "r"(rn)); \
		rval; \
	})
#define mtdcrx(rn, val) \
	({	\
		asm volatile("mtdcrx %0,%1" : : "r"(rn), "r" (val)); \
	})

/* 440GP/440GX SDRAM controller DCRs */
#define DCRN_SDRAM0_CFGADDR				0x010
#define DCRN_SDRAM0_CFGDATA				0x011

#define SDRAM0_READ(offset) ({\
	mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
	mfdcr(DCRN_SDRAM0_CFGDATA); })
#define SDRAM0_WRITE(offset, data) ({\
	mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
	mtdcr(DCRN_SDRAM0_CFGDATA, data); })

#define 	SDRAM0_B0CR				0x40
#define 	SDRAM0_B1CR				0x44
#define 	SDRAM0_B2CR				0x48
#define 	SDRAM0_B3CR				0x4c

static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR,
					    SDRAM0_B2CR, SDRAM0_B3CR };

#define			SDRAM_CONFIG_BANK_ENABLE        0x00000001
#define			SDRAM_CONFIG_SIZE_MASK          0x000e0000
#define			SDRAM_CONFIG_BANK_SIZE(reg)	\
	(0x00400000 << ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17))

/* 440GP External Bus Controller (EBC) */
#define DCRN_EBC0_CFGADDR				0x012
#define DCRN_EBC0_CFGDATA				0x013
#define   EBC_NUM_BANKS					  8
#define   EBC_B0CR					  0x00
#define   EBC_B1CR					  0x01
#define   EBC_B2CR					  0x02
#define   EBC_B3CR					  0x03
#define   EBC_B4CR					  0x04
#define   EBC_B5CR					  0x05
#define   EBC_B6CR					  0x06
#define   EBC_B7CR					  0x07
#define   EBC_BXCR(n)					  (n)
#define	    EBC_BXCR_BAS				    0xfff00000
#define	    EBC_BXCR_BS				  	    0x000e0000
#define	    EBC_BXCR_BANK_SIZE(reg) \
	(0x100000 << (((reg) & EBC_BXCR_BS) >> 17))
#define	    EBC_BXCR_BU				  	    0x00018000
#define	      EBC_BXCR_BU_OFF			  	      0x00000000
#define	      EBC_BXCR_BU_RO			  	      0x00008000
#define	      EBC_BXCR_BU_WO			  	      0x00010000
#define	      EBC_BXCR_BU_RW			  	      0x00018000
#define	    EBC_BXCR_BW				  	    0x00006000
#define   EBC_B0AP					  0x10
#define   EBC_B1AP					  0x11
#define   EBC_B2AP					  0x12
#define   EBC_B3AP					  0x13
#define   EBC_B4AP					  0x14
#define   EBC_B5AP					  0x15
#define   EBC_B6AP					  0x16
#define   EBC_B7AP					  0x17
#define   EBC_BXAP(n)					  (0x10+(n))
#define   EBC_BEAR					  0x20
#define   EBC_BESR					  0x21
#define   EBC_CFG					  0x23
#define   EBC_CID					  0x24

/* 440GP Clock, PM, chip control */
#define DCRN_CPC0_SR					0x0b0
#define DCRN_CPC0_ER					0x0b1
#define DCRN_CPC0_FR					0x0b2
#define DCRN_CPC0_SYS0					0x0e0
#define	  CPC0_SYS0_TUNE				  0xffc00000
#define	  CPC0_SYS0_FBDV_MASK				  0x003c0000

Annotation

Implementation Notes