arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
Source file repositories/reference/linux-study-clean/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi- Extension
.dtsi- Size
- 4482 bytes
- Lines
- 190
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
&ifc {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,ifc";
interrupts = <16 2 0 0 20 2 0 0>;
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,bsc9131-immr", "simple-bus";
bus-frequency = <0>; // Filled out by uboot.
ecm-law@0 {
compatible = "fsl,ecm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <12>;
};
ecm@1000 {
compatible = "fsl,bsc9131-ecm", "fsl,ecm";
reg = <0x1000 0x1000>;
interrupts = <16 2 0 0>;
};
memory-controller@2000 {
compatible = "fsl,bsc9131-memory-controller";
reg = <0x2000 0x1000>;
interrupts = <16 2 0 0>;
};
/include/ "pq3-i2c-0.dtsi"
i2c@3000 {
interrupts = <17 2 0 0>;
};
/include/ "pq3-i2c-1.dtsi"
i2c@3100 {
interrupts = <17 2 0 0>;
};
/include/ "pq3-duart-0.dtsi"
serial0: serial@4500 {
interrupts = <18 2 0 0>;
};
serial1: serial@4600 {
interrupts = <18 2 0 0 >;
};
/include/ "pq3-espi-0.dtsi"
spi0: spi@7000 {
fsl,espi-num-chipselects = <1>;
interrupts = <22 0x2 0 0>;
};
/include/ "pq3-gpio-0.dtsi"
gpio-controller@f000 {
interrupts = <19 0x2 0 0>;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,bsc9131-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x40000>; // L2,256K
interrupts = <16 2 0 0>;
};
/include/ "pq3-dma-0.dtsi"
Annotation
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.