arch/powerpc/boot/dts/fsl/gef_ppc9a.dts
Source file repositories/reference/linux-study-clean/arch/powerpc/boot/dts/fsl/gef_ppc9a.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/boot/dts/fsl/gef_ppc9a.dts- Extension
.dts- Size
- 4439 bytes
- Lines
- 217
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* GE PPC9A Device Tree Source
*
* Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
*
* Based on: SBS CM6 Device Tree Source
* Copyright 2007 SBS Technologies GmbH & Co. KG
* And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
* Copyright 2006 Freescale Semiconductor Inc.
*/
/*
* Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
*/
/include/ "mpc8641si-pre.dtsi"
/ {
model = "GEF_PPC9A";
compatible = "gef,ppc9a";
memory {
device_type = "memory";
reg = <0x0 0x40000000>; // set by uboot
};
lbc: localbus@fef05000 {
reg = <0xfef05000 0x1000>;
ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
1 0 0xe8000000 0x08000000 // Paged Flash 0
2 0 0xe0000000 0x08000000 // Paged Flash 1
3 0 0xfc100000 0x00020000 // NVRAM
4 0 0xfc000000 0x00008000 // FPGA
5 0 0xfc008000 0x00008000 // AFIX FPGA
6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
/* flash@0,0 is a mirror of part of the memory in flash@1,0
flash@0,0 {
compatible = "gef,ppc9a-firmware-mirror", "cfi-flash";
reg = <0x0 0x0 0x1000000>;
bank-width = <4>;
device-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "firmware";
reg = <0x0 0x1000000>;
read-only;
};
};
*/
flash@1,0 {
compatible = "gef,ppc9a-paged-flash", "cfi-flash";
reg = <0x1 0x0 0x8000000>;
bank-width = <4>;
device-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "user";
reg = <0x0 0x7800000>;
};
partition@7800000 {
label = "firmware";
reg = <0x7800000 0x800000>;
read-only;
Annotation
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.