arch/powerpc/boot/dts/fsl/mpc8572ds_36b.dts

File Facts

System

Linux kernel

Corpus path

arch/powerpc/boot/dts/fsl/mpc8572ds_36b.dts

Extension

.dts

Size

2045 bytes

Lines

87

Domain

Architecture Layer

Bucket

arch/powerpc

Inferred role

Architecture Layer: configuration, schema, or hardware description

Status

atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * MPC8572DS Device Tree Source (36-bit address map)
 *
 * Copyright 2007-2009 Freescale Semiconductor Inc.
 */

/include/ "mpc8572si-pre.dtsi"

/ {
	model = "fsl,MPC8572DS";
	compatible = "fsl,MPC8572DS";

	memory {
		device_type = "memory";
	};

	board_lbc: lbc: localbus@fffe05000 {
		reg = <0xf 0xffe05000 0 0x1000>;

		ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
			  0x1 0x0 0xf 0xe0000000 0x08000000
			  0x2 0x0 0xf 0xffa00000 0x00040000
			  0x3 0x0 0xf 0xffdf0000 0x00008000
			  0x4 0x0 0xf 0xffa40000 0x00040000
			  0x5 0x0 0xf 0xffa80000 0x00040000
			  0x6 0x0 0xf 0xffac0000 0x00040000>;
	};

	board_soc: soc: soc8572@fffe00000 {
		ranges = <0x0 0xf 0xffe00000 0x100000>;
	};

	board_pci0: pci0: pcie@fffe08000 {
		reg = <0xf 0xffe08000 0 0x1000>;
		ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000>;
		pcie@0 {
			ranges = <0x2000000 0x0 0xe0000000
				  0x2000000 0x0 0xe0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x10000>;
		};
	};

	pci1: pcie@fffe09000 {
		reg = <0xf 0xffe09000 0 0x1000>;
		ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000>;
		pcie@0 {
			ranges = <0x2000000 0x0 0xe0000000
				  0x2000000 0x0 0xe0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x10000>;
		};
	};

	pci2: pcie@fffe0a000 {
		reg = <0xf 0xffe0a000 0 0x1000>;
		ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x00010000>;
		pcie@0 {
			ranges = <0x2000000 0x0 0xe0000000
				  0x2000000 0x0 0xe0000000

Annotation

• Atlas domain: Architecture Layer / arch/powerpc.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.