arch/powerpc/boot/dts/fsl/mpc8572ds_camp_core0.dts
Source file repositories/reference/linux-study-clean/arch/powerpc/boot/dts/fsl/mpc8572ds_camp_core0.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/boot/dts/fsl/mpc8572ds_camp_core0.dts- Extension
.dts- Size
- 1468 bytes
- Lines
- 79
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* MPC8572 DS Core0 Device Tree Source in CAMP mode.
*
* In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
* can be shared, all the other devices must be assigned to one core only.
* This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0,
* eth1, crypto, pci0, pci1.
*
* Copyright 2007-2009 Freescale Semiconductor Inc.
*/
/include/ "mpc8572ds.dts"
/ {
model = "fsl,MPC8572DS";
compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
cpus {
PowerPC,8572@0 {
};
PowerPC,8572@1 {
status = "disabled";
};
};
localbus@ffe05000 {
status = "disabled";
};
soc8572@ffe00000 {
serial@4600 {
status = "disabled";
};
dma@c300 {
status = "disabled";
};
gpio-controller@f000 {
};
l2-cache-controller@20000 {
cache-size = <0x80000>; // L2, 512K
};
ethernet@26000 {
status = "disabled";
};
mdio@26520 {
status = "disabled";
};
ethernet@27000 {
status = "disabled";
};
mdio@27520 {
status = "disabled";
};
pic@40000 {
protected-sources = <
31 32 33 37 38 39 /* enet2 enet3 */
76 77 78 79 26 42 /* dma2 pci2 serial*/
0xe4 0xe5 0xe6 0xe7 /* msi */
>;
};
msi@41600 {
msi-available-ranges = <0 0x80>;
interrupts = <
0xe0 0 0 0
0xe1 0 0 0
0xe2 0 0 0
0xe3 0 0 0>;
};
Annotation
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.