arch/powerpc/boot/dts/fsl/mpc8572ds_camp_core1.dts

Source file repositories/reference/linux-study-clean/arch/powerpc/boot/dts/fsl/mpc8572ds_camp_core1.dts

File Facts

System
Linux kernel
Corpus path
arch/powerpc/boot/dts/fsl/mpc8572ds_camp_core1.dts
Extension
.dts
Size
2137 bytes
Lines
112
Domain
Architecture Layer
Bucket
arch/powerpc
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * MPC8572 DS Core1 Device Tree Source in CAMP mode.
 *
 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
 * can be shared, all the other devices must be assigned to one core only.
 * This dts allows core1 to have l2, dma2, eth2, eth3, pci2, msi.
 *
 * Please note to add "-b 1" for core1's dts compiling.
 *
 * Copyright 2007-2009 Freescale Semiconductor Inc.
 */

/include/ "mpc8572ds.dts"

/ {
	model = "fsl,MPC8572DS";
	compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";

	cpus {
		PowerPC,8572@0 {
			status = "disabled";
		};
		PowerPC,8572@1 {
		};
	};

	localbus@ffe05000 {
		status = "disabled";
	};

	soc8572@ffe00000 {
		ecm-law@0 {
			status = "disabled";
		};
		ecm@1000 {
			status = "disabled";
		};
		memory-controller@2000 {
			status = "disabled";
		};
		memory-controller@6000 {
			status = "disabled";
		};
		i2c@3000 {
			status = "disabled";
		};
		i2c@3100 {
			status = "disabled";
		};
		serial@4500 {
			status = "disabled";
		};
		gpio-controller@f000 {
			status = "disabled";
		};
		l2-cache-controller@20000 {
			cache-size = <0x80000>;	// L2, 512K
		};
		dma@21300 {
			status = "disabled";
		};
		ethernet@24000 {
			status = "disabled";
		};
		ptp_clock@24e00 {
			status = "disabled";
		};
		ethernet@25000 {
			status = "disabled";

Annotation

Implementation Notes