arch/powerpc/boot/dts/fsl/p1020rdb-pc_camp_core0.dts

Source file repositories/reference/linux-study-clean/arch/powerpc/boot/dts/fsl/p1020rdb-pc_camp_core0.dts

File Facts

System
Linux kernel
Corpus path
arch/powerpc/boot/dts/fsl/p1020rdb-pc_camp_core0.dts
Extension
.dts
Size
1191 bytes
Lines
61
Domain
Architecture Layer
Bucket
arch/powerpc
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * P1020 RDB-PC  Core0 Device Tree Source in CAMP mode.
 *
 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
 * can be shared, all the other devices must be assigned to one core only.
 * This dts file allows core0 to have memory, l2, i2c, spi, gpio, tdm, dma, usb,
 * eth1, eth2, sdhc, crypto, global-util, message, pci0, pci1, msi.
 *
 * Please note to add "-b 0" for core0's dts compiling.
 *
 * Copyright 2012 Freescale Semiconductor Inc.
 */

/include/ "p1020rdb-pc_32b.dts"

/ {
	model = "fsl,P1020RDB-PC";
	compatible = "fsl,P1020RDB-PC";

	aliases {
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		serial0 = &serial0;
		pci0 = &pci0;
		pci1 = &pci1;
	};

	cpus {
		PowerPC,P1020@1 {
			status = "disabled";
		};
	};

	memory {
		device_type = "memory";
	};

	localbus@ffe05000 {
		status = "disabled";
	};

	soc@ffe00000 {
		serial1: serial@4600 {
			status = "disabled";
		};

		enet0: ethernet@b0000 {
			status = "disabled";
		};

		mpic: pic@40000 {
			protected-sources = <
			42 29 30 34	/* serial1, enet0-queue-group0 */
			17 18 24 45	/* enet0-queue-group1, crypto */
			>;
			pic-no-reset;
		};
	};
};

Annotation

Implementation Notes