arch/powerpc/boot/dts/fsl/p2020rdb-pc_36b.dts

Source file repositories/reference/linux-study-clean/arch/powerpc/boot/dts/fsl/p2020rdb-pc_36b.dts

File Facts

System: Linux kernel
Corpus path: arch/powerpc/boot/dts/fsl/p2020rdb-pc_36b.dts
Extension: .dts
Size: 3214 bytes
Lines: 97
Domain: Architecture Layer
Bucket: arch/powerpc
Inferred role: Architecture Layer: configuration, schema, or hardware description
Status: atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

/include/ "p2020si-pre.dtsi"

/ {
	model = "fsl,P2020RDB";
	compatible = "fsl,P2020RDB-PC";

	memory {
		device_type = "memory";
	};

	lbc: localbus@fffe05000 {
		reg = <0xf 0xffe05000 0 0x1000>;

		/* NOR and NAND Flashes */
		ranges = <0x0 0x0 0xf 0xef000000 0x01000000
			  0x1 0x0 0xf 0xff800000 0x00040000
			  0x2 0x0 0xf 0xffb00000 0x00020000
			  0x3 0x0 0xf 0xffa00000 0x00020000>;
	};

	soc: soc@fffe00000 {
		ranges = <0x0 0xf 0xffe00000 0x100000>;
	};

	pci2: pcie@fffe08000 {
		reg = <0xf 0xffe08000 0 0x1000>;
		status = "disabled";
	};

	pci1: pcie@fffe09000 {
		reg = <0xf 0xffe09000 0 0x1000>;
		ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
		pcie@0 {
			ranges = <0x2000000 0x0 0xe0000000
				  0x2000000 0x0 0xe0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};

	pci0: pcie@fffe0a000 {
		reg = <0xf 0xffe0a000 0 0x1000>;
		ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
		pcie@0 {
			ranges = <0x2000000 0x0 0xe0000000
				  0x2000000 0x0 0xe0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};
};

/include/ "p2020rdb-pc.dtsi"
/include/ "p2020si-post.dtsi"

Annotation

Atlas domain: Architecture Layer / arch/powerpc.
Implementation status: atlas-only.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.