arch/powerpc/boot/dts/fsp2.dts
Source file repositories/reference/linux-study-clean/arch/powerpc/boot/dts/fsp2.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/boot/dts/fsp2.dts- Extension
.dts- Size
- 13095 bytes
- Lines
- 614
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
/dts-v1/;
/ {
#address-cells = <2>;
#size-cells = <1>;
model = "ibm,fsp2";
compatible = "ibm,fsp2";
dcr-parent = <&{/cpus/cpu@0}>;
aliases {
ethernet0 = &EMAC0;
ethernet1 = &EMAC1;
serial0 = &UART0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
model = "PowerPC, 476FSP2";
reg = <0x0>;
clock-frequency = <0>; /* Filled in by cuboot */
timebase-frequency = <0>; /* Filled in by cuboot */
i-cache-line-size = <32>;
d-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-size = <32768>;
dcr-controller;
dcr-access-method = "native";
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by
cuboot */
};
clocks {
mmc_clk: mmc_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "mmc_clk";
};
};
UIC0: uic0 {
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
compatible = "ibm,uic";
interrupt-controller;
cell-index = <0>;
dcr-reg = <0x2c0 0x8>;
};
/* "interrupts" field is <bit level bit level>
first pair is non-critical, second is critical */
UIC1_0: uic1_0 {
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
compatible = "ibm,uic";
interrupt-controller;
cell-index = <1>;
dcr-reg = <0x2c8 0x8>;
Annotation
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.