arch/powerpc/boot/dts/iss4xx-mpic.dts
Source file repositories/reference/linux-study-clean/arch/powerpc/boot/dts/iss4xx-mpic.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/boot/dts/iss4xx-mpic.dts- Extension
.dts- Size
- 3837 bytes
- Lines
- 156
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
/dts-v1/;
/memreserve/ 0x01f00000 0x00100000;
/ {
#address-cells = <2>;
#size-cells = <1>;
model = "ibm,iss-4xx";
compatible = "ibm,iss-4xx";
dcr-parent = <&{/cpus/cpu@0}>;
aliases {
serial0 = &UART0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
model = "PowerPC,4xx"; // real CPU changed in sim
reg = <0>;
clock-frequency = <100000000>; // 100Mhz :-)
timebase-frequency = <100000000>;
i-cache-line-size = <32>;
d-cache-line-size = <32>;
i-cache-size = <32768>;
d-cache-size = <32768>;
dcr-controller;
dcr-access-method = "native";
status = "okay";
};
cpu@1 {
device_type = "cpu";
model = "PowerPC,4xx"; // real CPU changed in sim
reg = <1>;
clock-frequency = <100000000>; // 100Mhz :-)
timebase-frequency = <100000000>;
i-cache-line-size = <32>;
d-cache-line-size = <32>;
i-cache-size = <32768>;
d-cache-size = <32768>;
dcr-controller;
dcr-access-method = "native";
status = "disabled";
enable-method = "spin-table";
cpu-release-addr = <0 0x01f00100>;
};
cpu@2 {
device_type = "cpu";
model = "PowerPC,4xx"; // real CPU changed in sim
reg = <2>;
clock-frequency = <100000000>; // 100Mhz :-)
timebase-frequency = <100000000>;
i-cache-line-size = <32>;
d-cache-line-size = <32>;
i-cache-size = <32768>;
d-cache-size = <32768>;
dcr-controller;
dcr-access-method = "native";
status = "disabled";
enable-method = "spin-table";
cpu-release-addr = <0 0x01f00200>;
};
cpu@3 {
device_type = "cpu";
model = "PowerPC,4xx"; // real CPU changed in sim
reg = <3>;
clock-frequency = <100000000>; // 100Mhz :-)
Annotation
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.