arch/powerpc/boot/dts/mpc5121.dtsi
Source file repositories/reference/linux-study-clean/arch/powerpc/boot/dts/mpc5121.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/boot/dts/mpc5121.dtsi- Extension
.dtsi- Size
- 12039 bytes
- Lines
- 527
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/clock/mpc512x-clock.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* base MPC5121 Device Tree Source
*
* Copyright 2007-2008 Freescale Semiconductor Inc.
*/
#include <dt-bindings/clock/mpc512x-clock.h>
/dts-v1/;
/ {
model = "mpc5121";
compatible = "fsl,mpc5121";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&ipic>;
aliases {
ethernet0 = ð0;
pci = &pci;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,5121@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <0x20>; /* 32 bytes */
i-cache-line-size = <0x20>; /* 32 bytes */
d-cache-size = <0x8000>; /* L1, 32K */
i-cache-size = <0x8000>; /* L1, 32K */
timebase-frequency = <49500000>;/* 49.5 MHz (csb/4) */
bus-frequency = <198000000>; /* 198 MHz csb bus */
clock-frequency = <396000000>; /* 396 MHz ppc core */
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x10000000>; /* 256MB at 0 */
};
mbx@20000000 {
compatible = "fsl,mpc5121-mbx";
reg = <0x20000000 0x4000>;
interrupts = <66 0x8>;
clocks = <&clks MPC512x_CLK_MBX_BUS>,
<&clks MPC512x_CLK_MBX_3D>,
<&clks MPC512x_CLK_MBX>;
clock-names = "mbx-bus", "mbx-3d", "mbx";
};
sram@30000000 {
compatible = "fsl,mpc5121-sram";
reg = <0x30000000 0x20000>; /* 128K at 0x30000000 */
};
nfc@40000000 {
compatible = "fsl,mpc5121-nfc";
reg = <0x40000000 0x100000>; /* 1M at 0x40000000 */
interrupts = <6 8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&clks MPC512x_CLK_NFC>;
clock-names = "ipg";
};
Annotation
- Immediate include surface: `dt-bindings/clock/mpc512x-clock.h`.
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.