arch/powerpc/boot/dts/taishan.dts
Source file repositories/reference/linux-study-clean/arch/powerpc/boot/dts/taishan.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/boot/dts/taishan.dts- Extension
.dts- Size
- 10834 bytes
- Lines
- 428
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
/dts-v1/;
/ {
#address-cells = <2>;
#size-cells = <1>;
model = "amcc,taishan";
compatible = "amcc,taishan";
dcr-parent = <&{/cpus/cpu@0}>;
aliases {
ethernet0 = &EMAC2;
ethernet1 = &EMAC3;
serial0 = &UART0;
serial1 = &UART1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
model = "PowerPC,440GX";
reg = <0x00000000>;
clock-frequency = <800000000>; // 800MHz
timebase-frequency = <0>; // Filled in by zImage
i-cache-line-size = <50>;
d-cache-line-size = <50>;
i-cache-size = <32768>; /* 32 kB */
d-cache-size = <32768>; /* 32 kB */
dcr-controller;
dcr-access-method = "native";
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
};
UICB0: interrupt-controller-base {
compatible = "ibm,uic-440gx", "ibm,uic";
interrupt-controller;
cell-index = <3>;
dcr-reg = <0x200 0x009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
};
UIC0: interrupt-controller0 {
compatible = "ibm,uic-440gx", "ibm,uic";
interrupt-controller;
cell-index = <0>;
dcr-reg = <0x0c0 0x009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
interrupts = <0x1 0x4 0x0 0x4>; /* cascade - first non-critical */
interrupt-parent = <&UICB0>;
};
UIC1: interrupt-controller1 {
compatible = "ibm,uic-440gx", "ibm,uic";
interrupt-controller;
cell-index = <1>;
dcr-reg = <0x0d0 0x009>;
Annotation
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.