arch/powerpc/include/asm/book3s/32/mmu-hash.h

Source file repositories/reference/linux-study-clean/arch/powerpc/include/asm/book3s/32/mmu-hash.h

File Facts

System
Linux kernel
Corpus path
arch/powerpc/include/asm/book3s/32/mmu-hash.h
Extension
.h
Size
6340 bytes
Lines
240
Domain
Architecture Layer
Bucket
arch/powerpc
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ppc_bat {
	u32 batu;
	u32 batl;
};
#endif /* !__ASSEMBLER__ */

/*
 * Hash table
 */

/* Values for PP (assumes Ks=0, Kp=1) */
#define PP_RWXX	0	/* Supervisor read/write, User none */
#define PP_RWRX 1	/* Supervisor read/write, User read */
#define PP_RWRW 2	/* Supervisor read/write, User read/write */
#define PP_RXRX 3	/* Supervisor read,       User read */

/* Values for Segment Registers */
#define SR_NX	0x10000000	/* No Execute */
#define SR_KP	0x20000000	/* User key */
#define SR_KS	0x40000000	/* Supervisor key */

#ifdef __ASSEMBLER__

#include <asm/asm-offsets.h>

.macro uus_addi sr reg1 reg2 imm
	.if NUM_USER_SEGMENTS > \sr
	addi	\reg1,\reg2,\imm
	.endif
.endm

.macro uus_mtsr sr reg1
	.if NUM_USER_SEGMENTS > \sr
	mtsr	\sr, \reg1
	.endif
.endm

/*
 * This isync() shouldn't be necessary as the kernel is not excepted to run
 * any instruction in userspace soon after the update of segments and 'rfi'
 * instruction is used to return to userspace, but hash based cores
 * (at least G3) seem to exhibit a random behaviour when the 'isync' is not
 * there. 603 cores don't have this behaviour so don't do the 'isync' as it
 * saves several CPU cycles.
 */
.macro uus_isync
#ifdef CONFIG_PPC_BOOK3S_604
BEGIN_MMU_FTR_SECTION
	isync
END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
#endif
.endm

.macro update_user_segments_by_4 tmp1 tmp2 tmp3 tmp4
	uus_addi	1, \tmp2, \tmp1, 0x111
	uus_addi	2, \tmp3, \tmp1, 0x222
	uus_addi	3, \tmp4, \tmp1, 0x333

	uus_mtsr	0, \tmp1
	uus_mtsr	1, \tmp2
	uus_mtsr	2, \tmp3
	uus_mtsr	3, \tmp4

	uus_addi	4, \tmp1, \tmp1, 0x444
	uus_addi	5, \tmp2, \tmp2, 0x444
	uus_addi	6, \tmp3, \tmp3, 0x444
	uus_addi	7, \tmp4, \tmp4, 0x444

	uus_mtsr	4, \tmp1
	uus_mtsr	5, \tmp2
	uus_mtsr	6, \tmp3
	uus_mtsr	7, \tmp4

	uus_addi	8, \tmp1, \tmp1, 0x444
	uus_addi	9, \tmp2, \tmp2, 0x444
	uus_addi	10, \tmp3, \tmp3, 0x444
	uus_addi	11, \tmp4, \tmp4, 0x444

	uus_mtsr	8, \tmp1
	uus_mtsr	9, \tmp2
	uus_mtsr	10, \tmp3
	uus_mtsr	11, \tmp4

	uus_addi	12, \tmp1, \tmp1, 0x444
	uus_addi	13, \tmp2, \tmp2, 0x444
	uus_addi	14, \tmp3, \tmp3, 0x444
	uus_addi	15, \tmp4, \tmp4, 0x444

	uus_mtsr	12, \tmp1
	uus_mtsr	13, \tmp2

Annotation

Implementation Notes