arch/powerpc/include/asm/book3s/64/hash-4k.h

Source file repositories/reference/linux-study-clean/arch/powerpc/include/asm/book3s/64/hash-4k.h

File Facts

System
Linux kernel
Corpus path
arch/powerpc/include/asm/book3s/64/hash-4k.h
Extension
.h
Size
5238 bytes
Lines
174
Domain
Architecture Layer
Bucket
arch/powerpc
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _ASM_POWERPC_BOOK3S_64_HASH_4K_H
#define _ASM_POWERPC_BOOK3S_64_HASH_4K_H

#define H_PTE_INDEX_SIZE  9  // size: 8B << 9 = 4KB, maps: 2^9 x   4KB =   2MB
#define H_PMD_INDEX_SIZE  7  // size: 8B << 7 = 1KB, maps: 2^7 x   2MB = 256MB
#define H_PUD_INDEX_SIZE  9  // size: 8B << 9 = 4KB, maps: 2^9 x 256MB = 128GB
#define H_PGD_INDEX_SIZE  9  // size: 8B << 9 = 4KB, maps: 2^9 x 128GB =  64TB

/*
 * Each context is 512TB. But on 4k we restrict our max TASK size to 64TB
 * Hence also limit max EA bits to 64TB.
 */
#define MAX_EA_BITS_PER_CONTEXT		46


/*
 * Our page table limit us to 64TB. For 64TB physical memory, we only need 64GB
 * of vmemmap space. To better support sparse memory layout, we use 61TB
 * linear map range, 1TB of vmalloc, 1TB of I/O and 1TB of vmememmap.
 */
#define REGION_SHIFT		(40)
#define H_KERN_MAP_SIZE		(ASM_CONST(1) << REGION_SHIFT)

/*
 * Limits the linear mapping range
 */
#define H_MAX_PHYSMEM_BITS	46

/*
 * Define the address range of the kernel non-linear virtual area (61TB)
 */
#define H_KERN_VIRT_START	ASM_CONST(0xc0003d0000000000)

#ifndef __ASSEMBLER__
#define H_PTE_TABLE_SIZE	(sizeof(pte_t) << H_PTE_INDEX_SIZE)
#define H_PMD_TABLE_SIZE	(sizeof(pmd_t) << H_PMD_INDEX_SIZE)
#define H_PUD_TABLE_SIZE	(sizeof(pud_t) << H_PUD_INDEX_SIZE)
#define H_PGD_TABLE_SIZE	(sizeof(pgd_t) << H_PGD_INDEX_SIZE)

#define H_PAGE_F_GIX_SHIFT	_PAGE_PA_MAX
#define H_PAGE_F_SECOND		_RPAGE_PKEY_BIT0 /* HPTE is in 2ndary HPTEG */
#define H_PAGE_F_GIX		(_RPAGE_RPN43 | _RPAGE_RPN42 | _RPAGE_RPN41)
#define H_PAGE_BUSY		_RPAGE_RSV1
#define H_PAGE_HASHPTE		_RPAGE_PKEY_BIT4

/* PTE flags to conserve for HPTE identification */
#define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_HASHPTE | \
			 H_PAGE_F_SECOND | H_PAGE_F_GIX)
/*
 * Not supported by 4k linux page size
 */
#define H_PAGE_4K_PFN	0x0
#define H_PAGE_THP_HUGE 0x0
#define H_PAGE_COMBO	0x0

/* 8 bytes per each pte entry */
#define H_PTE_FRAG_SIZE_SHIFT  (H_PTE_INDEX_SIZE + 3)
#define H_PTE_FRAG_NR	(PAGE_SIZE >> H_PTE_FRAG_SIZE_SHIFT)
#define H_PMD_FRAG_SIZE_SHIFT  (H_PMD_INDEX_SIZE + 3)
#define H_PMD_FRAG_NR	(PAGE_SIZE >> H_PMD_FRAG_SIZE_SHIFT)

/* memory key bits, only 8 keys supported */
#define H_PTE_PKEY_BIT4	0
#define H_PTE_PKEY_BIT3	0
#define H_PTE_PKEY_BIT2	_RPAGE_PKEY_BIT3
#define H_PTE_PKEY_BIT1	_RPAGE_PKEY_BIT2
#define H_PTE_PKEY_BIT0	_RPAGE_PKEY_BIT1


/*
 * On all 4K setups, remap_4k_pfn() equates to remap_pfn_range()
 */
#define remap_4k_pfn(vma, addr, pfn, prot)	\
	remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))

/*
 * With 4K page size the real_pte machinery is all nops.
 */
static inline real_pte_t __real_pte(pte_t pte, pte_t *ptep, int offset)
{
	return (real_pte_t){pte};
}

#define __rpte_to_pte(r)	((r).pte)

static inline unsigned long __rpte_to_hidx(real_pte_t rpte, unsigned long index)
{
	return pte_val(__rpte_to_pte(rpte)) >> H_PAGE_F_GIX_SHIFT;
}

Annotation

Implementation Notes