arch/powerpc/include/asm/cache.h
Source file repositories/reference/linux-study-clean/arch/powerpc/include/asm/cache.h
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/include/asm/cache.h- Extension
.h- Size
- 2972 bytes
- Lines
- 151
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
struct ppc_cache_infostruct ppc64_cachesfunction l1_dcache_shiftfunction l1_dcache_bytesfunction l1_icache_shiftfunction l1_icache_bytesfunction l1_dcache_shiftfunction l1_dcache_bytesfunction l1_icache_shiftfunction l1_icache_bytesfunction dcbzfunction dcbifunction dcbffunction dcbstfunction icbifunction iccci
Annotated Snippet
struct ppc_cache_info {
u32 size;
u32 line_size;
u32 block_size; /* L1 only */
u32 log_block_size;
u32 blocks_per_page;
u32 sets;
u32 assoc;
};
struct ppc64_caches {
struct ppc_cache_info l1d;
struct ppc_cache_info l1i;
struct ppc_cache_info l2;
struct ppc_cache_info l3;
};
extern struct ppc64_caches ppc64_caches;
static inline u32 l1_dcache_shift(void)
{
return ppc64_caches.l1d.log_block_size;
}
static inline u32 l1_dcache_bytes(void)
{
return ppc64_caches.l1d.block_size;
}
static inline u32 l1_icache_shift(void)
{
return ppc64_caches.l1i.log_block_size;
}
static inline u32 l1_icache_bytes(void)
{
return ppc64_caches.l1i.block_size;
}
#else
static inline u32 l1_dcache_shift(void)
{
return L1_CACHE_SHIFT;
}
static inline u32 l1_dcache_bytes(void)
{
return L1_CACHE_BYTES;
}
static inline u32 l1_icache_shift(void)
{
return L1_CACHE_SHIFT;
}
static inline u32 l1_icache_bytes(void)
{
return L1_CACHE_BYTES;
}
#endif
#define __read_mostly __section(".data..read_mostly")
#ifdef CONFIG_PPC_BOOK3S_32
extern long _get_L2CR(void);
extern long _get_L3CR(void);
extern void _set_L2CR(unsigned long);
extern void _set_L3CR(unsigned long);
#else
#define _get_L2CR() 0L
#define _get_L3CR() 0L
#define _set_L2CR(val) do { } while(0)
#define _set_L3CR(val) do { } while(0)
#endif
static inline void dcbz(void *addr)
{
__asm__ __volatile__ ("dcbz 0, %0" : : "r"(addr) : "memory");
}
static inline void dcbi(void *addr)
{
__asm__ __volatile__ ("dcbi 0, %0" : : "r"(addr) : "memory");
}
static inline void dcbf(void *addr)
{
__asm__ __volatile__ ("dcbf 0, %0" : : "r"(addr) : "memory");
}
Annotation
- Detected declarations: `struct ppc_cache_info`, `struct ppc64_caches`, `function l1_dcache_shift`, `function l1_dcache_bytes`, `function l1_icache_shift`, `function l1_icache_bytes`, `function l1_dcache_shift`, `function l1_dcache_bytes`, `function l1_icache_shift`, `function l1_icache_bytes`.
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.