arch/powerpc/include/asm/cell-pmu.h
Source file repositories/reference/linux-study-clean/arch/powerpc/include/asm/cell-pmu.h
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/include/asm/cell-pmu.h- Extension
.h- Size
- 891 bytes
- Lines
- 39
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
enum pm_reg_name
Annotated Snippet
#ifndef __ASM_CELL_PMU_H__
#define __ASM_CELL_PMU_H__
/* The Cell PMU has four hardware performance counters, which can be
* configured as four 32-bit counters or eight 16-bit counters.
*/
#define NR_PHYS_CTRS 4
#define NR_CTRS (NR_PHYS_CTRS * 2)
/* Macros for the pm_control register. */
#define CBE_PM_16BIT_CTR(ctr) (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1))))
/* Macros for the trace_address register. */
#define CBE_PM_TRACE_BUF_EMPTY 0x00000400
enum pm_reg_name {
group_control,
debug_bus_control,
trace_address,
ext_tr_timer,
pm_status,
pm_control,
pm_interval,
pm_start_stop,
};
#endif /* __ASM_CELL_PMU_H__ */
Annotation
- Detected declarations: `enum pm_reg_name`.
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.