arch/powerpc/include/asm/imc-pmu.h
Source file repositories/reference/linux-study-clean/arch/powerpc/include/asm/imc-pmu.h
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/include/asm/imc-pmu.h- Extension
.h- Size
- 4007 bytes
- Lines
- 173
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/perf_event.hlinux/slab.hlinux/of.hlinux/io.hasm/opal.h
Detected Declarations
struct imc_mem_infostruct imc_eventsstruct trace_imc_datastruct imc_pmustruct imc_pmu_ref
Annotated Snippet
struct imc_mem_info {
u64 *vbase;
u32 id;
};
/*
* Place holder for nest pmu events and values.
*/
struct imc_events {
u32 value;
char *name;
char *unit;
char *scale;
};
/*
* Trace IMC hardware updates a 64bytes record on
* Core Performance Monitoring Counter (CPMC)
* overflow. Here is the layout for the trace imc record
*
* DW 0 : Timebase
* DW 1 : Program Counter
* DW 2 : PIDR information
* DW 3 : CPMC1
* DW 4 : CPMC2
* DW 5 : CPMC3
* Dw 6 : CPMC4
* DW 7 : Timebase
* .....
*
* The following is the data structure to hold trace imc data.
*/
struct trace_imc_data {
__be64 tb1;
__be64 ip;
__be64 val;
__be64 cpmc1;
__be64 cpmc2;
__be64 cpmc3;
__be64 cpmc4;
__be64 tb2;
};
/* Event attribute array index */
#define IMC_FORMAT_ATTR 0
#define IMC_EVENT_ATTR 1
#define IMC_CPUMASK_ATTR 2
#define IMC_NULL_ATTR 3
/* PMU Format attribute macros */
#define IMC_EVENT_OFFSET_MASK 0xffffffffULL
/*
* Macro to mask bits 0:21 of first double word(which is the timebase) to
* compare with 8th double word (timebase) of trace imc record data.
*/
#define IMC_TRACE_RECORD_TB1_MASK 0x3ffffffffffULL
/*
* Bit 0:1 in third DW of IMC trace record
* specifies the MSR[HV PR] values.
*/
#define IMC_TRACE_RECORD_VAL_HVPR(x) ((x) >> 62)
/*
* Device tree parser code detects IMC pmu support and
* registers new IMC pmus. This structure will hold the
* pmu functions, events, counter memory information
* and attrs for each imc pmu and will be referenced at
* the time of pmu registration.
*/
struct imc_pmu {
struct pmu pmu;
struct imc_mem_info *mem_info;
struct imc_events *events;
/*
* Attribute groups for the PMU. Slot 0 used for
* format attribute, slot 1 used for cpusmask attribute,
* slot 2 used for event attribute. Slot 3 keep as
* NULL.
*/
const struct attribute_group *attr_groups[4];
u32 counter_mem_size;
int domain;
/*
* flag to notify whether the memory is mmaped
* or allocated by kernel.
*/
bool imc_counter_mmaped;
};
Annotation
- Immediate include surface: `linux/perf_event.h`, `linux/slab.h`, `linux/of.h`, `linux/io.h`, `asm/opal.h`.
- Detected declarations: `struct imc_mem_info`, `struct imc_events`, `struct trace_imc_data`, `struct imc_pmu`, `struct imc_pmu_ref`.
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.