arch/powerpc/include/asm/mpic_msgr.h
Source file repositories/reference/linux-study-clean/arch/powerpc/include/asm/mpic_msgr.h
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/include/asm/mpic_msgr.h- Extension
.h- Size
- 3441 bytes
- Lines
- 130
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/types.hlinux/spinlock.hasm/smp.hasm/io.h
Detected Declarations
struct mpic_msgrfunction mpic_msgr_writefunction mpic_msgr_readfunction mpic_msgr_clearfunction mpic_msgr_set_destinationfunction mpic_msgr_get_irq
Annotated Snippet
struct mpic_msgr {
u32 __iomem *base;
u32 __iomem *mer;
int irq;
unsigned char in_use;
raw_spinlock_t lock;
int num;
};
/* Get a message register
*
* @reg_num: the MPIC message register to get
*
* A pointer to the message register is returned. If
* the message register asked for is already in use, then
* EBUSY is returned. If the number given is not associated
* with an actual message register, then ENODEV is returned.
* Successfully getting the register marks it as in use.
*/
extern struct mpic_msgr *mpic_msgr_get(unsigned int reg_num);
/* Relinquish a message register
*
* @msgr: the message register to return
*
* Disables the given message register and marks it as free.
* After this call has completed successully the message
* register is available to be acquired by a call to
* mpic_msgr_get.
*/
extern void mpic_msgr_put(struct mpic_msgr *msgr);
/* Enable a message register
*
* @msgr: the message register to enable
*
* The given message register is enabled for sending
* messages.
*/
extern void mpic_msgr_enable(struct mpic_msgr *msgr);
/* Disable a message register
*
* @msgr: the message register to disable
*
* The given message register is disabled for sending
* messages.
*/
extern void mpic_msgr_disable(struct mpic_msgr *msgr);
/* Write a message to a message register
*
* @msgr: the message register to write to
* @message: the message to write
*
* The given 32-bit message is written to the given message
* register. Writing to an enabled message registers fires
* an interrupt.
*/
static inline void mpic_msgr_write(struct mpic_msgr *msgr, u32 message)
{
out_be32(msgr->base, message);
}
/* Read a message from a message register
*
* @msgr: the message register to read from
*
* Returns the 32-bit value currently in the given message register.
* Upon reading the register any interrupts for that register are
* cleared.
*/
static inline u32 mpic_msgr_read(struct mpic_msgr *msgr)
{
return in_be32(msgr->base);
}
/* Clear a message register
*
* @msgr: the message register to clear
*
* Clears any interrupts associated with the given message register.
*/
static inline void mpic_msgr_clear(struct mpic_msgr *msgr)
{
(void) mpic_msgr_read(msgr);
}
/* Set the destination CPU for the message register
*
Annotation
- Immediate include surface: `linux/types.h`, `linux/spinlock.h`, `asm/smp.h`, `asm/io.h`.
- Detected declarations: `struct mpic_msgr`, `function mpic_msgr_write`, `function mpic_msgr_read`, `function mpic_msgr_clear`, `function mpic_msgr_set_destination`, `function mpic_msgr_get_irq`.
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.