arch/powerpc/include/asm/reg_booke.h

Source file repositories/reference/linux-study-clean/arch/powerpc/include/asm/reg_booke.h

File Facts

System
Linux kernel
Corpus path
arch/powerpc/include/asm/reg_booke.h
Extension
.h
Size
28723 bytes
Lines
592
Domain
Architecture Layer
Bucket
arch/powerpc
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifdef __KERNEL__
#ifndef __ASM_POWERPC_REG_BOOKE_H__
#define __ASM_POWERPC_REG_BOOKE_H__

#include <asm/ppc-opcode.h>

/* Machine State Register (MSR) Fields */
#define MSR_GS_LG	28	/* Guest state */
#define MSR_UCLE_LG	26	/* User-mode cache lock enable */
#define MSR_SPE_LG	25	/* Enable SPE */
#define MSR_DWE_LG	10	/* Debug Wait Enable */
#define MSR_UBLE_LG	10	/* BTB lock enable (e500) */
#define MSR_IS_LG	MSR_IR_LG /* Instruction Space */
#define MSR_DS_LG	MSR_DR_LG /* Data Space */
#define MSR_PMM_LG	2	/* Performance monitor mark bit */
#define MSR_CM_LG	31	/* Computation Mode (0=32-bit, 1=64-bit) */

#define MSR_GS		__MASK(MSR_GS_LG)
#define MSR_UCLE	__MASK(MSR_UCLE_LG)
#define MSR_SPE		__MASK(MSR_SPE_LG)
#define MSR_DWE		__MASK(MSR_DWE_LG)
#define MSR_UBLE	__MASK(MSR_UBLE_LG)
#define MSR_IS		__MASK(MSR_IS_LG)
#define MSR_DS		__MASK(MSR_DS_LG)
#define MSR_PMM		__MASK(MSR_PMM_LG)
#define MSR_CM		__MASK(MSR_CM_LG)

#if defined(CONFIG_PPC_BOOK3E_64)
#define MSR_64BIT	MSR_CM

#define MSR_		(MSR_ME | MSR_RI | MSR_CE)
#define MSR_KERNEL	(MSR_ | MSR_64BIT)
#define MSR_USER32	(MSR_ | MSR_PR | MSR_EE)
#define MSR_USER64	(MSR_USER32 | MSR_64BIT)
#else
#define MSR_KERNEL	(MSR_ME|MSR_RI|MSR_CE)
#define MSR_USER	(MSR_KERNEL|MSR_PR|MSR_EE)
#endif

/* Special Purpose Registers (SPRNs)*/
#define SPRN_DECAR	0x036	/* Decrementer Auto Reload Register */
#define SPRN_IVPR	0x03F	/* Interrupt Vector Prefix Register */
#define SPRN_USPRG0	0x100	/* User Special Purpose Register General 0 */
#define SPRN_SPRG3R	0x103	/* Special Purpose Register General 3 Read */
#define SPRN_SPRG4R	0x104	/* Special Purpose Register General 4 Read */
#define SPRN_SPRG5R	0x105	/* Special Purpose Register General 5 Read */
#define SPRN_SPRG6R	0x106	/* Special Purpose Register General 6 Read */
#define SPRN_SPRG7R	0x107	/* Special Purpose Register General 7 Read */
#define SPRN_SPRG4W	0x114	/* Special Purpose Register General 4 Write */
#define SPRN_SPRG5W	0x115	/* Special Purpose Register General 5 Write */
#define SPRN_SPRG6W	0x116	/* Special Purpose Register General 6 Write */
#define SPRN_SPRG7W	0x117	/* Special Purpose Register General 7 Write */
#define SPRN_EPCR	0x133	/* Embedded Processor Control Register */
#define SPRN_DBCR2	0x136	/* Debug Control Register 2 */
#define SPRN_DBCR4	0x233	/* Debug Control Register 4 */
#define SPRN_MSRP	0x137	/* MSR Protect Register */
#define SPRN_IAC3	0x13A	/* Instruction Address Compare 3 */
#define SPRN_IAC4	0x13B	/* Instruction Address Compare 4 */
#define SPRN_DVC1	0x13E	/* Data Value Compare Register 1 */
#define SPRN_DVC2	0x13F	/* Data Value Compare Register 2 */
#define SPRN_LPID	0x152	/* Logical Partition ID */
#define SPRN_MAS8	0x155	/* MMU Assist Register 8 */
#define SPRN_TLB0PS	0x158	/* TLB 0 Page Size Register */
#define SPRN_TLB1PS	0x159	/* TLB 1 Page Size Register */
#define SPRN_MAS5_MAS6	0x15c	/* MMU Assist Register 5 || 6 */
#define SPRN_MAS8_MAS1	0x15d	/* MMU Assist Register 8 || 1 */
#define SPRN_EPTCFG	0x15e	/* Embedded Page Table Config */
#define SPRN_GSPRG0	0x170	/* Guest SPRG0 */
#define SPRN_GSPRG1	0x171	/* Guest SPRG1 */
#define SPRN_GSPRG2	0x172	/* Guest SPRG2 */
#define SPRN_GSPRG3	0x173	/* Guest SPRG3 */
#define SPRN_MAS7_MAS3	0x174	/* MMU Assist Register 7 || 3 */
#define SPRN_MAS0_MAS1	0x175	/* MMU Assist Register 0 || 1 */
#define SPRN_GSRR0	0x17A	/* Guest SRR0 */
#define SPRN_GSRR1	0x17B	/* Guest SRR1 */
#define SPRN_GEPR	0x17C	/* Guest EPR */
#define SPRN_GDEAR	0x17D	/* Guest DEAR */
#define SPRN_GPIR	0x17E	/* Guest PIR */
#define SPRN_GESR	0x17F	/* Guest Exception Syndrome Register */
#define SPRN_IVOR0	0x190	/* Interrupt Vector Offset Register 0 */
#define SPRN_IVOR1	0x191	/* Interrupt Vector Offset Register 1 */
#define SPRN_IVOR2	0x192	/* Interrupt Vector Offset Register 2 */
#define SPRN_IVOR3	0x193	/* Interrupt Vector Offset Register 3 */
#define SPRN_IVOR4	0x194	/* Interrupt Vector Offset Register 4 */
#define SPRN_IVOR5	0x195	/* Interrupt Vector Offset Register 5 */
#define SPRN_IVOR6	0x196	/* Interrupt Vector Offset Register 6 */
#define SPRN_IVOR7	0x197	/* Interrupt Vector Offset Register 7 */
#define SPRN_IVOR8	0x198	/* Interrupt Vector Offset Register 8 */
#define SPRN_IVOR9	0x199	/* Interrupt Vector Offset Register 9 */
#define SPRN_IVOR10	0x19A	/* Interrupt Vector Offset Register 10 */

Annotation

Implementation Notes