arch/powerpc/include/asm/synch.h
Source file repositories/reference/linux-study-clean/arch/powerpc/include/asm/synch.h
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/include/asm/synch.h- Extension
.h- Size
- 2159 bytes
- Lines
- 74
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
asm/cputable.hasm/feature-fixups.hasm/ppc-opcode.h
Detected Declarations
function eieiofunction isyncfunction ppc_after_tlbiel_barrier
Annotated Snippet
#ifndef _ASM_POWERPC_SYNCH_H
#define _ASM_POWERPC_SYNCH_H
#ifdef __KERNEL__
#include <asm/cputable.h>
#include <asm/feature-fixups.h>
#include <asm/ppc-opcode.h>
#ifndef __ASSEMBLER__
extern unsigned int __start___lwsync_fixup, __stop___lwsync_fixup;
extern void do_lwsync_fixups(unsigned long value, void *fixup_start,
void *fixup_end);
static inline void eieio(void)
{
if (IS_ENABLED(CONFIG_BOOKE))
__asm__ __volatile__ ("mbar" : : : "memory");
else
__asm__ __volatile__ ("eieio" : : : "memory");
}
static inline void isync(void)
{
__asm__ __volatile__ ("isync" : : : "memory");
}
static inline void ppc_after_tlbiel_barrier(void)
{
asm volatile("ptesync": : :"memory");
/*
* POWER9, POWER10 need a cp_abort after tlbiel to ensure the copy is
* invalidated correctly. If this is not done, the paste can take data
* from the physical address that was translated at copy time.
*
* POWER9 in practice does not need this, because address spaces with
* accelerators mapped will use tlbie (which does invalidate the copy)
* to invalidate translations. It's not possible to limit POWER10 this
* way due to local copy-paste.
*/
asm volatile(ASM_FTR_IFSET(PPC_CP_ABORT, "", %0) : : "i" (CPU_FTR_ARCH_31) : "memory");
}
#endif /* __ASSEMBLER__ */
#if defined(__powerpc64__)
# define LWSYNC lwsync
#elif defined(CONFIG_PPC_E500)
# define LWSYNC \
START_LWSYNC_SECTION(96); \
sync; \
MAKE_LWSYNC_SECTION_ENTRY(96, __lwsync_fixup);
#else
# define LWSYNC sync
#endif
#ifdef CONFIG_SMP
#define __PPC_ACQUIRE_BARRIER \
START_LWSYNC_SECTION(97); \
isync; \
MAKE_LWSYNC_SECTION_ENTRY(97, __lwsync_fixup);
#define PPC_ACQUIRE_BARRIER "\n" stringify_in_c(__PPC_ACQUIRE_BARRIER)
#define PPC_RELEASE_BARRIER stringify_in_c(LWSYNC) "\n"
#define PPC_ATOMIC_ENTRY_BARRIER "\n" stringify_in_c(sync) "\n"
#define PPC_ATOMIC_EXIT_BARRIER "\n" stringify_in_c(sync) "\n"
#else
#define PPC_ACQUIRE_BARRIER
#define PPC_RELEASE_BARRIER
#define PPC_ATOMIC_ENTRY_BARRIER
#define PPC_ATOMIC_EXIT_BARRIER
#endif
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_SYNCH_H */
Annotation
- Immediate include surface: `asm/cputable.h`, `asm/feature-fixups.h`, `asm/ppc-opcode.h`.
- Detected declarations: `function eieio`, `function isync`, `function ppc_after_tlbiel_barrier`.
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.