arch/powerpc/include/uapi/asm/tm.h

File Facts

System

Linux kernel

Corpus path

arch/powerpc/include/uapi/asm/tm.h

Extension

.h

Size

734 bytes

Lines

22

Domain

Architecture Layer

Bucket

arch/powerpc

Inferred role

Architecture Layer: implementation source

Status

source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _ASM_POWERPC_TM_H
#define _ASM_POWERPC_TM_H

/* Reason codes describing kernel causes for transaction aborts.  By
 * convention, bit0 is copied to TEXASR[56] (IBM bit 7) which is set if
 * the failure is persistent.  PAPR saves 0xff-0xe0 for the hypervisor.
 */
#define TM_CAUSE_PERSISTENT	0x01
#define TM_CAUSE_KVM_RESCHED	0xe0  /* From PAPR */
#define TM_CAUSE_KVM_FAC_UNAV	0xe2  /* From PAPR */
#define TM_CAUSE_RESCHED	0xde
#define TM_CAUSE_TLBI		0xdc
#define TM_CAUSE_FAC_UNAV	0xda
#define TM_CAUSE_SYSCALL	0xd8
#define TM_CAUSE_MISC		0xd6  /* future use */
#define TM_CAUSE_SIGNAL		0xd4
#define TM_CAUSE_ALIGNMENT	0xd2
#define TM_CAUSE_EMULATE	0xd0

#endif

Annotation

• Atlas domain: Architecture Layer / arch/powerpc.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.