arch/powerpc/kernel/head_85xx.S

Source file repositories/reference/linux-study-clean/arch/powerpc/kernel/head_85xx.S

File Facts

System
Linux kernel
Corpus path
arch/powerpc/kernel/head_85xx.S
Extension
.S
Size
29548 bytes
Lines
1169
Domain
Architecture Layer
Bucket
arch/powerpc
Inferred role
Architecture Layer: arch/powerpc
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

lis	r4,start_kernel@h
	ori	r4,r4,start_kernel@l
	lis	r3,MSR_KERNEL@h
	ori	r3,r3,MSR_KERNEL@l
	mtspr	SPRN_SRR0,r4
	mtspr	SPRN_SRR1,r3
	rfi			/* change context and jump to start_kernel */

/* Macros to hide the PTE size differences
 *
 * FIND_PTE -- walks the page tables given EA & pgdir pointer
 *   r10 -- free
 *   r11 -- PGDIR pointer
 *   r12 -- free
 *   r13 -- EA of fault
 *   label 2: is the bailout case
 *
 * if we find the pte (fall through):
 *   r11 is low pte word
 *   r12 is pointer to the pte
 *   r10 is the pshift from the PGD, if we're a hugepage
 */
#ifdef CONFIG_HUGETLB_PAGE
#define FIND_PTE	\
	rlwinm	r12, r13, 14, 18, 28;	/* Compute pgdir/pmd offset */	\
	add	r12, r11, r12;						\
	lwz	r11, 4(r12);		/* Get pgd/pmd entry */		\
	rlwinm.	r10, r11, 32 - _PAGE_PSIZE_SHIFT, 0x1e; /* get tsize*/	\
	bne	1000f;			/* Huge page (leaf entry) */	\
	rlwinm.	r12, r11, 0, 0, 20;	/* Extract pt base address */	\
	beq	2f;			/* Bail if no table */		\
	rlwimi	r12, r13, 23, 20, 28;	/* Compute pte address */	\
	li	r10, 0;			/* clear r10 */			\
	lwz	r11, 4(r12);		/* Get pte entry */		\
1000:
#else
#define FIND_PTE	\
	rlwinm	r12, r13, 14, 18, 28;	/* Compute pgdir/pmd offset */	\
	add	r12, r11, r12;						\
	lwz	r11, 4(r12);		/* Get pgd/pmd entry */		\
	rlwinm.	r12, r11, 0, 0, 20;	/* Extract pt base address */	\
	beq	2f;			/* Bail if no table */		\
	rlwimi	r12, r13, 23, 20, 28;	/* Compute pte address */	\
	lwz	r11, 4(r12);		/* Get pte entry */
#endif /* HUGEPAGE */

/*
 * Interrupt vector entry code
 *
 * The Book E MMUs are always on so we don't need to handle
 * interrupts in real mode as with previous PPC processors. In
 * this case we handle interrupts in the kernel virtual address
 * space.
 *
 * Interrupt vectors are dynamically placed relative to the
 * interrupt prefix as determined by the address of interrupt_base.
 * The interrupt vectors offsets are programmed using the labels
 * for each interrupt vector entry.
 *
 * Interrupt vectors must be aligned on a 16 byte boundary.
 * We align on a 32 byte cache line boundary for good measure.
 */

interrupt_base:
	/* Critical Input Interrupt */
	CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception)

	/* Machine Check Interrupt */
	MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)

Annotation

Implementation Notes