arch/powerpc/kernel/idle_book3s.S
Source file repositories/reference/linux-study-clean/arch/powerpc/kernel/idle_book3s.S
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/kernel/idle_book3s.S- Extension
.S- Size
- 5709 bytes
- Lines
- 219
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: arch/powerpc
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
asm/ppc_asm.hasm/asm-offsets.hasm/ppc-opcode.hasm/cpuidle.hasm/thread_info.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/ppc-opcode.h>
#include <asm/cpuidle.h>
#include <asm/thread_info.h> /* TLF_NAPPING */
#ifdef CONFIG_PPC_P7_NAP
/*
* Desired PSSCR in r3
*
* No state will be lost regardless of wakeup mechanism (interrupt or NIA).
*
* An EC=0 type wakeup will return with a value of 0. SRESET wakeup (which can
* happen with xscom SRESET and possibly MCE) may clobber volatiles except LR,
* and must blr, to return to caller with r3 set according to caller's expected
* return code (for Book3S/64 that is SRR1).
*/
_GLOBAL(isa300_idle_stop_noloss)
mtspr SPRN_PSSCR,r3
PPC_STOP
li r3,0
blr
/*
* Desired PSSCR in r3
*
* GPRs may be lost, so they are saved here. Wakeup is by interrupt only.
* The SRESET wakeup returns to this function's caller by calling
* idle_return_gpr_loss with r3 set to desired return value.
*
* A wakeup without GPR loss may alteratively be handled as in
* isa300_idle_stop_noloss and blr directly, as an optimisation.
*
* The caller is responsible for saving/restoring SPRs, MSR, timebase,
* etc.
*/
_GLOBAL(isa300_idle_stop_mayloss)
mtspr SPRN_PSSCR,r3
std r1,PACAR1(r13)
mflr r4
mfcr r5
/*
* Use the stack red zone rather than a new frame for saving regs since
* in the case of no GPR loss the wakeup code branches directly back to
* the caller without deallocating the stack frame first.
*/
std r2,-8*1(r1)
std r14,-8*2(r1)
std r15,-8*3(r1)
std r16,-8*4(r1)
std r17,-8*5(r1)
std r18,-8*6(r1)
std r19,-8*7(r1)
std r20,-8*8(r1)
std r21,-8*9(r1)
std r22,-8*10(r1)
std r23,-8*11(r1)
std r24,-8*12(r1)
std r25,-8*13(r1)
std r26,-8*14(r1)
std r27,-8*15(r1)
std r28,-8*16(r1)
std r29,-8*17(r1)
std r30,-8*18(r1)
std r31,-8*19(r1)
std r4,-8*20(r1)
std r5,-8*21(r1)
/* 168 bytes */
PPC_STOP
b . /* catch bugs */
Annotation
- Immediate include surface: `asm/ppc_asm.h`, `asm/asm-offsets.h`, `asm/ppc-opcode.h`, `asm/cpuidle.h`, `asm/thread_info.h`.
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.