arch/powerpc/kernel/pci-hotplug.c
Source file repositories/reference/linux-study-clean/arch/powerpc/kernel/pci-hotplug.c
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/kernel/pci-hotplug.c- Extension
.c- Size
- 4981 bytes
- Lines
- 182
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/pci.hlinux/export.hlinux/of.hasm/pci-bridge.hasm/ppc-pci.hasm/firmware.hasm/eeh.h
Detected Declarations
function Copyrightfunction list_for_each_entryfunction pcibios_release_devicefunction pci_hp_remove_devicesfunction traverse_siblings_and_scan_slotfunction pci_hp_add_devicesexport pci_find_bus_by_nodeexport pci_hp_remove_devicesexport pci_hp_add_devices
Annotated Snippet
if (!((class >> 8) == PCI_CLASS_BRIDGE_PCI)) {
slotno = PCI_SLOT(PCI_DN(start->child)->devfn);
pci_scan_slot(bus, PCI_DEVFN(slotno, 0));
return;
}
}
/* Iterate all siblings */
for_each_child_of_node(start, dn) {
class = 0;
if (!of_property_read_u32(start->child, "class-code", &class)) {
/* Call of pci_scan_slot on each sibling-nodes/bridge-ports */
if ((class >> 8) == PCI_CLASS_BRIDGE_PCI) {
slotno = PCI_SLOT(PCI_DN(dn)->devfn);
pci_scan_slot(bus, PCI_DEVFN(slotno, 0));
}
}
}
}
/**
* pci_hp_add_devices - adds new pci devices to bus
* @bus: the indicated PCI bus
*
* This routine will find and fixup new pci devices under
* the indicated bus. This routine presumes that there
* might already be some devices under this bridge, so
* it carefully tries to add only new devices. (And that
* is how this routine differs from other, similar pcibios
* routines.)
*/
void pci_hp_add_devices(struct pci_bus *bus)
{
int mode, max;
struct pci_dev *dev;
struct pci_controller *phb;
struct device_node *dn = pci_bus_to_OF_node(bus);
if (!dn)
return;
phb = pci_bus_to_host(bus);
mode = PCI_PROBE_NORMAL;
if (phb->controller_ops.probe_mode)
mode = phb->controller_ops.probe_mode(bus);
if (mode == PCI_PROBE_DEVTREE) {
/* use ofdt-based probe */
of_rescan_bus(dn, bus);
} else if (mode == PCI_PROBE_NORMAL &&
dn->child && PCI_DN(dn->child)) {
/*
* Use legacy probe. In the partial hotplug case, we
* probably have grandchildren devices unplugged. So
* we don't check the return value from pci_scan_slot() in
* order for fully rescan all the way down to pick them up.
* They can have been removed during partial hotplug.
*/
traverse_siblings_and_scan_slot(dn, bus);
max = bus->busn_res.start;
/*
* Scan bridges that are already configured. We don't touch
* them unless they are misconfigured (which will be done in
* the second scan below).
*/
for_each_pci_bridge(dev, bus)
max = pci_scan_bridge(bus, dev, max, 0);
/* Scan bridges that need to be reconfigured */
for_each_pci_bridge(dev, bus)
max = pci_scan_bridge(bus, dev, max, 1);
}
pcibios_finish_adding_to_bus(bus);
}
EXPORT_SYMBOL_GPL(pci_hp_add_devices);
Annotation
- Immediate include surface: `linux/pci.h`, `linux/export.h`, `linux/of.h`, `asm/pci-bridge.h`, `asm/ppc-pci.h`, `asm/firmware.h`, `asm/eeh.h`.
- Detected declarations: `function Copyright`, `function list_for_each_entry`, `function pcibios_release_device`, `function pci_hp_remove_devices`, `function traverse_siblings_and_scan_slot`, `function pci_hp_add_devices`, `export pci_find_bus_by_node`, `export pci_hp_remove_devices`, `export pci_hp_add_devices`.
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: integration implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.